Binary tester for logic circuit sub-assemblies

Claim 1

A TESTING DEVICE FOR LOGIC CIRCUIT SUB-ASSEMBLIES OF ANY DESIGN ACCORDING TO CORRESPONDING STANDARD SUBASSEMBLIES AND HAVING RECESS TERMINALS INCLUDING INPUT TERMINALS AND OUTPUT TERMINALS THE NUMBER OF SAID RECESS TERMINALS BEING LESS THAN OR EQUAL TO A GIVEN MAXIMUM NUMBER, COMPRISING FOR EACH ACCESS TERMINAL OF A SUBASSEMBLY HAVING SAID MAXIMUM NUMBER OF TERMINALS, A TRIGGER STAGE, SAID TRIGGER STAGES BEING ASSOCIATED AS A BINARY COUNTER, A COMPARSION CIRCUIT FORMED BY AN ANDNOT GATE HAVING TWO INPUTS AND ONE INPUT SAID A RELAY HAVING TWO PAIRS OF CONTACTS, SAID RELAY BEING ADAPTED TO CONNECT SAID ACCESS TERMINAL AND THE LIKE TERMINAL OF A CORRESPONDING STANDARD SUB-ASSEMBLY IN PARALLEL ON THE ONE HAND TO AN OUTPUT OF SAID TRIGGER STAGE VIA THE MAKE CONTACTS OF SAID RELAY, ON THE OTHER HAND TO AN OUTPUT AND SAID TRIGGER STAGE VIA THE BREAK CONTACTS OF SAID RELAY AND COMPRISING MEANS FOR SELECTIVELY ENERGIZING THE RELAYS CORRESPONDING TO INPUT TERMINALS OF SUB-ASSEMBLIES OF ANY GIVEN DESIGN, SQUARE-WAVE-SIGNAL GENERATOR MEANS FOR STEPPING SAID COUNTER THROUGH THE AGENCY OF AN INHIBITOR CIRCUIT WHICH IS INHIBITED BY THE PRESSENCE AT THE OUTPUT OF AT LEAST ONE OF SAID COMPARISION CIRCUITS OF A SIGNAL INDICATING A DISCREPANCY BETWEEN THE OUTPUT SIGNAL ASSOCIATED WITH THE SUB-ASSEMBLY BEING TESTED AND THE OUTPUT SIGNAL ASSCOCIATED WITH THE CORRESPONDING STANDARD SUB-ASSEMBLY.