Programmable logic device with hierarchical interconnection resources

Claim 2

An integrated circuit comprising: a plurality of super-regions of programmable logic disposed on the integrated circuit in a two-dimensional array of rows and columns, each of the super-regions including: a plurality of regions of programmable logic, each of the regions including a plurality of subregions of programmable logic, each of the subregions being programmable to perform any of a plurality of logic functions on a plurality of input signals applied to the subregion to produce an output signal which is indicative of the result of performance of the logic function on the input signals; and a plurality of local feedback interconnection conductors associated with each of said regions and configured to convey output signals of the subregions in the associated region so that said output signals on said local feedback interconnection conductors are available for programmable application to any of said subregions in the associated region as said input signals; a plurality of inter-region interconnection conductors configured to convey signals to the regions in the super-region so that said signals on said inter-region interconnection conductors are available for programmable application to any of said subregions in the super-region as said input signals; a plurality of horizontal inter-super-region interconnection conductors associated with each of said rows and configured to convey signals to, from, and between super-regions in the associated row; a plurality of vertical inter-super-region interconnection conductors associated with each of said columns and configured to convey signals to, from, and between super-regions in the associated column; a first plurality of programmable logic connectors configured to selectively apply signals on the inter-region interconnection conductors associated with a super-region directly to each of said subregions in said super-region as said input signals without routing through any of said local feedback interconnection conductors; a second plurality of programmable logic connectors configured to selectively apply signals on the inter-super-region interconnection conductors associated with a super-region to each of said subregions in said super-region as said input signals without routing through any of said local feedback interconnection conductors; and a third plurality of programmable logic connectors configured to selectively interconnect said horizontal and vertical inter-super-region conductors.

Claim 3

The circuit defined in claim 1 further comprising: a fourth plurality of programmable logic connectors configured to selectively apply signals on said horizontal and vertical inter-super-region interconnection conductors to said inter-region interconnection conductors.

Claim 4

The circuit defined in claim 1 wherein one of the inter-super-region conductors includes axially distinct segments, and further comprising programmable circuitry configured to programmably connect two of the axially distinct segments and to amplify a signal passing from one of the segments through the programmable circuitry to the other of the segments.

Claim 5

An integrated circuit comprising: a plurality of super-regions of programmable logic disposed on the integrated circuit in a two-dimensional array of rows and columns, each of the super-regions including: a plurality of regions of programmable logic, each of the regions including a plurality of subregions of programmable logic, each of the subregions being programmable to perform any of a plurality of logic functions on a plurality of input signals applied to the subregion to produce an output signal which is indicative of the result of performance of the logic function on the input signals; and a plurality of input interconnection conductors associated with each of said regions and configured to convey signals to the subregions in the associated region so that said signals on said input interconnection conductors are available for programmable application to any of said subregions in the associated region as said input signals; a plurality of inter-region interconnection conductors programmably connected to said input interconnection conductors and configured to convey signals to the regions in the super-region so that said signals on said inter-region interconnection conductors are available for programmable application to any of said subregions in the super-region as said input signals; a plurality of horizontal inter-super-region interconnection conductors associated with each of said rows and configured to convey signals to, from, and between super-regions in the associated row, said horizontal inter-super-region interconnection conductors being programmably connected to said input interconnection conductors; a plurality of vertical inter-super-region interconnection conductors associated with each of said columns and configured to convey signals to, from, and between super-regions in the associated column, said vertical inter-super-region interconnection conductors being programmably connected to said input interconnection conductors; a first plurality of programmable logic connectors configured to selectively apply signals on said horizontal and vertical inter-super-region interconnection conductors to any of the subregions in a super-region adjacent to said inter-super-region conductors as said input signals by routing through the input conductors associated with said subregions and without routing through any of said inter-region interconnection conductors; a second plurality of programmable logic connectors configured to selectively apply signals on said inter-region interconnection conductors to each of said subregions in a region as said input signals by routing through the input conductors associated with said subregions; and a third plurality of programmable logic connectors configured to selectively interconnect said horizontal and vertical inter-super-region interconnection conductors.

Claim 6

An integrated circuit comprising: a plurality of super-regions of programmable logic disposed on the integrated circuit in a two-dimensional array of rows and columns, each of the super-regions including: a plurality of regions of programmable logic, each of the regions including a plurality of subregions of programmable logic, each of the subregions being programmable to perform any of a plurality of logic functions on a plurality of input signals applied to the subregion to produce an output signal which is indicative of the result of performance of the logic function on the input signals; and a plurality of input interconnection conductors associated with each of said regions and configured to convey signals to the subregions in the associated region so that said signals on said input interconnection conductors are available for programmable application to any of said subregions in the associated region as said input signals; a plurality of inter-region interconnection conductors programmably connected to said input interconnection conductors and configured to convey signals to the regions in the super-region so that said signals on said inter-region interconnection conductors are available for programmable application to any of said subregions in the super-region as said input signals; a plurality of horizontal inter-super-region interconnection conductors associated with each of said rows and configured to convey signals to, from, and between super-regions in the associated row, said horizontal inter-super-region interconnection conductors being programmably connected to said input interconnection conductors; a plurality of vertical inter-super-region interconnection conductors associated with each of said columns and configured to convey signals to, from, and between super-regions in the associated column, said vertical inter-super-region interconnection conductors being programmably connected to said input interconnection conductors; a first plurality of programmable logic connectors configured to selectively apply signals on said horizontal and vertical inter-super-region interconnection conductors to any of the subregions in a super-region adjacent to said inter-super-region conductors as said input signals by routing through the input conductors associated with said subregions and without routing through any of said inter-region interconnection conductors; a second plurality of programmable logic connectors configured to selectively apply signals on said inter-region interconnection conductors to each of said subregions in a region as said input signals by routing through the input conductors associated with said subregions; and a third plurality of programmable logic connectors configured to selectively interconnect said horizontal and vertical inter-super-region interconnection conductors.

Claim 7

The circuit defined in claim 4 further comprising: a fourth plurality of programmable logic connectors configured to selectively apply signals on said horizontal and vertical inter-super-region interconnection conductors to said inter-region interconnection conductors.

Claim 8

A programmable logic device comprising: a plurality of super-regions of programmable logic disposed on the programmable logic device in a two-dimensional array of rows and columns, each of the super-regions including: a plurality of regions of programmable logic, each of the regions including a plurality of subregions of programmable logic, each of the subregions being programmable to perform any of a plurality of logic functions on a plurality of input signals applied to the subregion to produce an output signal which is indicative of the result of performance of the logic function on the input signals; region-feeding interconnection conductors associated with each of said regions and configured to convey signals to all of the subregions in the associated region for programmable application to any of said subregions as said input signals, said region-feeding interconnection conductors running substantially parallel to a first axis of said two-dimensional array; and a plurality of inter-region interconnection conductors associated with each of said regions and configured to convey signals for programmable application to any of said region-feeding interconnection conductors in the associated region, said inter-region interconnection conductors running substantially parallel to a second axis of said two-dimensional array that is substantially perpendicular to the first axis, routing through a region-feeding interconnection conductor associated with a subregion being the sole routing available on said device for applying a signal from any of said inter-region interconnection conductors to that subregion as one of said input signals; and a plurality of inter-super-region interconnection conductors configured to convey signals for programmable application to said inter-region interconnection conductors, said inter-super-region interconnection conductors running substantially parallel to the first axis of said two-dimensional array, routing through an inter-region interconnection conductor associated with a super-region and a region-feeding interconnection conductor associated with a subregion in that super-region being the sole routing available on said device for applying a signal from any of said inter-super-region interconnection conductors to that subregion as one of said input signals.

Claim 9

A programmable logic device comprising: a plurality of super-regions of programmable logic disposed on the programmable logic device in a two-dimensional array of rows and columns, each of the super-regions including: a plurality of regions of programmable logic, each of the regions including a plurality of subregions of programmable logic, each of the subregions being programmable to perform any of a plurality of logic functions on a plurality of input signals applied to the subregion to produce an output signal which is indicative of the result of performance of the logic function on the input signals; region-feeding interconnection conductors associated with each of said regions and configured to convey signals to all of the subregions in the associated region for programmable application to any of said subregions as said input signals, said region-feeding interconnection conductors running substantially parallel to a first axis of said two-dimensional array; and a plurality of inter-region interconnection conductors associated with each of said regions and configured to convey signals for programmable application to any of said region-feeding interconnection conductors in the associated region, said inter-region interconnection conductors running substantially parallel to a second axis of said two-dimensional array that is substantially perpendicular to the first axis, routing through a region-feeding interconnection conductor associated with a subregion being the sole routing available on said device for applying a signal from any of said inter-region interconnection conductors to that subregion as one of said input signals; and a plurality of inter-super-region interconnection conductors configured to convey signals for programmable application to said inter-region interconnection conductors, said inter-super-region interconnection conductors running substantially parallel to the first axis of said two-dimensional array, routing through an inter-region interconnection conductor associated with a super-region and a region-feeding interconnection conductor associated with a subregion in that super-region being the sole routing available on said device for applying a signal from any of said inter-super-region interconnection conductors to that subregion as one of said input signals.

Claim 10

The programmable logic device defined in claim 6 further comprising: a plurality of programmable logic connectors configured to selectively apply said output signals of each of said subregions in an associated region directly to said inter-super-region interconnection conductors without routing through inter-region interconnection conductors associated with said region.

Claim 11

The programmable logic device defined in claim 6 further comprising: a plurality of programmable logic connectors configured to selectively apply signals on said inter-super-region interconnection conductors to said inter-region interconnection conductors.

Claim 12

The programmable logic device defined in claim 6 wherein each of the super-regions further comprises: a plurality of programmable logic connectors configured to selectively apply signals on said inter-region interconnection conductors to said region-feeding interconnection conductors.

Claim 13

The programmable logic device defined in claim 6 wherein each of the super-regions further comprises: a plurality of programmable logic connectors configured to selectively apply said output signals of each of said subregions in an associated region to said inter-region interconnection conductors associated with said region.

Claim 14

A programmable logic device comprising: a plurality of regions of programmable logic disposed on the programmable logic device in a two-dimensional array of rows and columns, each of the regions including: a plurality of subregions of programmable logic, each of the subregions being programmable to perform any of a plurality of logic functions on a plurality of input signals applied to the subregion to produce an output signal which is indicative of the result of performance of the logic function on the input signals; a plurality of input interconnection conductors associated with each of said subregions and configured to convey signals for programmable application to any of said subregions in the associated region as said input signals, said input interconnection conductors running substantially parallel to a first axis of said two-dimensional array; a plurality of region-feeding interconnection conductors associated with each of said subregions in the region and configured to convey signals for programmable application to said input interconnection conductors in that region, said region-feeding interconnection conductors running substantially parallel to a second axis of said two-dimensional array that is substantially perpendicular to the first axis, routing through an input interconnection conductor associated with a subregion being the sole routing available on said device for applying a signal from any of said region-feeding interconnection conductors to that subregion as one of said input signals; and a plurality of inter-region interconnection conductors programmably connected to the region-feeding interconnection conductors and configured to programmably distribute signals among the regions, said inter-region interconnection conductors running substantially parallel to said first axis of said two-dimensional array, routing through a region-feeding interconnection conductor associated with a region and an input interconnection conductor associated with a subregion in that region being the sole routing available on said device for applying a signal from any of said inter-region interconnection conductors to that subregion as one of said input signals.

Claim 15

A programmable logic device comprising: a plurality of regions of programmable logic disposed on the programmable logic device in a two-dimensional array of rows and columns, each of the regions including: a plurality of subregions of programmable logic, each of the subregions being programmable to perform any of a plurality of logic functions on a plurality of input signals applied to the subregion to produce an output signal which is indicative of the result of performance of the logic function on the input signals; a plurality of input interconnection conductors associated with each of said subregions and configured to convey signals for programmable application to any of said subregions in the associated region as said input signals, said input interconnection conductors running substantially parallel to a first axis of said two-dimensional array; a plurality of region-feeding interconnection conductors associated with each of said subregions in the region and configured to convey signals for programmable application to said input interconnection conductors in that region, said region-feeding interconnection conductors running substantially parallel to a second axis of said two-dimensional array that is substantially perpendicular to the first axis, routing through an input interconnection conductor associated with a subregion being the sole routing available on said device for applying a signal from any of said region-feeding interconnection conductors to that subregion as one of said input signals; and a plurality of inter-region interconnection conductors programmably connected to the region-feeding interconnection conductors and configured to programmably distribute signals among the regions, said inter-region interconnection conductors running substantially parallel to said first axis of said two-dimensional array, routing through a region-feeding interconnection conductor associated with a region and an input interconnection conductor associated with a subregion in that region being the sole routing available on said device for applying a signal from any of said inter-region interconnection conductors to that subregion as one of said input signals.

Claim 16

The programmable logic device defined in claim 11 further comprising: a plurality of programmable logic connectors configured to selectively apply said output signals of each of said subregions in an associated region directly to said inter-region interconnection conductors without routing through said region-feeding interconnection conductors in said associated region.

Claim 17

The programmable logic device defined in claim 11 further comprising: a plurality of programmable logic connectors configured to selectively apply signals on said inter-region interconnection conductors to said region-feeding interconnection conductors.

Claim 18

The programmable logic device defined in claim 11 wherein each of the regions further comprises: a plurality of programmable logic connectors configured to selectively apply signals on said region-feeding interconnection conductors to said input interconnection conductors.

Claim 19

The programmable logic device defined in claim 11 wherein each of the regions further comprises: a plurality of programmable logic connectors configured to selectively apply said output signals of each of said subregions in an associated region to said region-feeding interconnection conductors associated with said region.

Claim 20

A programmable logic device comprising: a plurality of regions of programmable logic disposed on the programmable logic device in a two-dimensional array of rows and columns, each of the regions including: a plurality of subregions of programmable logic, each of the subregions being programmable to perform any of a plurality of logic functions on a plurality of input signals applied to the subregion to produce an output signal which is indicative of the result of performance of the logic function on the input signals; a plurality of input interconnection conductors associated with each of said regions and configured to convey signals for programmable application to any of said subregions in the associated region as said input signals; a plurality of region-feeding interconnection conductors associated with the region for conveying signals between subregions in the region so that the signals on the region-feeding interconnection conductors are available for programmable application to any of said input conductors in an associated region; and a plurality of inter-region interconnection conductors associated with each of said regions, and configured to convey signals between regions for programmable application to any of said region-feeding interconnection conductors in an associated region; and a plurality of programmable logic connectors configured to selectively apply said output signals of each of said subregions in an associated region directly to said inter-region interconnection conductors without routing through said input interconnection conductors.

Claim 21

A programmable logic device comprising: a plurality of regions of programmable logic disposed on the programmable logic device in a two-dimensional array of rows and columns, each of the regions including: a plurality of subregions of programmable logic, each of the subregions being programmable to perform any of a plurality of logic functions on a plurality of input signals applied to the subregion to produce an output signal which is indicative of the result of performance of the logic function on the input signals; a plurality of input interconnection conductors associated with each of said regions and configured to convey signals for programmable application to any of said subregions in the associated region as said input signals; a plurality of region-feeding interconnection conductors associated with the region for conveying signals between subregions in the region so that the signals on the region-feeding interconnection conductors are available for programmable application to any of said input conductors in an associated region; and a plurality of inter-region interconnection conductors associated with each of said regions, and configured to convey signals between regions for programmable application to any of said region-feeding interconnection conductors in an associated region; and a plurality of programmable logic connectors configured to selectively apply said output signals of each of said subregions in an associated region directly to said inter-region interconnection conductors without routing through said input interconnection conductors.

Claim 22

The programmable logic device defined in claim 16 further comprising: a second plurality of programmable logic connectors configured to selectively apply signals on said inter-region interconnection conductors to said region-feeding interconnection conductors.

Claim 23

The programmable logic device defined in claim 16 wherein each of the regions further comprises: a second plurality of programmable logic connectors configured to selectively apply signals on said region-feeding interconnection conductors to said input interconnection conductors.

Claim 24

The programmable logic device defined in claim 16 wherein routing through an input interconnection conductor associated with a subregion is the sole routing available on said device for applying a signal from any of said inter-region interconnection conductors to that subregion as one of said input signals.

Claim 25

The programmable logic device defined in claim 16 wherein routing through a region-feeding interconnection conductor associated with a region and an input interconnection conductor associated with a subregion in that region is the sole routing available on said device for applying a signal from any of said inter-region interconnection conductors to that subregion as one of said input signals.