US5583452A
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US
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Tri-directional buffer
Assignee: Xilinx Inc
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Filing: 1995-10-26
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Granted: 1996-12-10
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Expires: 2015-10-26
Abstract
Abstract A configurable multi-directional buffer circuit for a programmable integrated circuit. The novel buffer circuit is a configurable multi-directional buffer circuit having one pair of inverters and having a first input/output line and a second input/output line and a third input line multiplexed with the first input/output line. The novel buffer circuit is configurable to allow a signal from the first input/output line to be driven over the second input/output line or configurable to allow a signal from the second input/output line to be driven over the first input/output line. The novel buffer circuit also allows a signal over the third input line to be driven over the second input/output line. In either case, only a single pair of inverter circuits are used. In an alternate embodiment, the novel buffer allows signal over a fourth input line to be driven over the first input/output line. The novel buffer is configurable to realize any of the above configurations using programmable memory cells and therefore is well suited for application within a programmable integrated circuit. Since the novel buffer utilizes only a single pair of inverters to provide the buffering, in any configuration, it does not contain unused driver circuitry when configured. Therefore, the novel buffer advantageously consumes a relatively small amount of substrate area.
Inventors
- 👤 Khue Duong
- 👤 Stephen M. Trimberger
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 21:59
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/1778; H03K19/17792; H03K19/17704; H03K19/17788
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
153 words
A buffer circuit comprising: a first input/output line coupled to a first transistor through a multiplexer and coupled to a second transistor; a second input/output line coupled to a third and fourth transistor; a third input line coupled to said first transistor through said multiplexer; a driver circuit coupled to said first transistor, said second transistor, said third transistor and said fourth transistor; and programable memory coupled to control said first transistor, said second transistor, said third transistor and said fourth transistor in configurations such that a signal from said first input/output line is driven by said driver circuit over said second input/output line in a first configuration, a signal from said second input/output line is driven by said driver circuit over said first input/output line in a second configuration, and a signal from said third input line is driven by said driver circuit over said second input/output line in a third configuration.
Claim 2
Dependent Claim
153 words
A buffer circuit comprising: a first input/output line coupled to a first transistor through a multiplexer and coupled to a second transistor; a second input/output line coupled to a third and fourth transistor; a third input line coupled to said first transistor through said multiplexer; a driver circuit coupled to said first transistor, said second transistor, said third transistor and said fourth transistor; and programable memory coupled to control said first transistor, said second transistor, said third transistor and said fourth transistor in configurations such that a signal from said first input/output line is driven by said driver circuit over said second input/output line in a first configuration, a signal from said second input/output line is driven by said driver circuit over said first input/output line in a second configuration, and a signal from said third input line is driven by said driver circuit over said second input/output line in a third configuration.
Claim 3
Dependent Claim
36 words
A buffer circuit as described in claim 1 wherein said multiplexer circuit further comprises a programable memory cell for selecting between said first input/output line and said third input line in said first and third configurations.
Claim 4
Dependent Claim
52 words
A buffer circuit as described in claim 1 wherein said programmable memory comprises a first memory cell and a second memory cell wherein said first memory cell is coupled to gates of said first and third transistors and said second memory cell is coupled to gates of said second and fourth transistors.
Claim 5
Dependent Claim
20 words
A buffer circuit as described in claim 1 wherein said driver circuit comprises a pair of serially coupled inverter circuits.
Claim 6
Dependent Claim
31 words
A buffer circuit as described in claim 3 wherein said first, second, third and fourth transistors are n-type transistors and wherein said first and second programmable memory cells are SRAM cells.
Claim 7
Dependent Claim
182 words
A buffer circuit comprising: a first input/output line coupled to a first transistor through a first multiplexer and coupled to a second transistor; a second input/output line coupled to a third transistor through a second multiplexer and coupled to a fourth transistor; a third input line coupled to said first transistor through said first multiplexer; a fourth input line coupled to said third transistor through said second multiplexer; a driver circuit coupled to said first transistor, said second transistor, said third transistor and said fourth transistor; and programmable memory coupled to control said first transistor, said second transistor, said third transistor and said fourth transistor in configurations such that a signal from said first input/output line is driven by said driver circuit over said second input/output line, a signal from said second input/output line is driven by said driver circuit over said first input/output line, a signal from said third input line is driven by said driver circuit over said second input/output line, and a signal from said fourth input line is driven by said driver circuit over said first input/output line.
Claim 8
Dependent Claim
182 words
A buffer circuit comprising: a first input/output line coupled to a first transistor through a first multiplexer and coupled to a second transistor; a second input/output line coupled to a third transistor through a second multiplexer and coupled to a fourth transistor; a third input line coupled to said first transistor through said first multiplexer; a fourth input line coupled to said third transistor through said second multiplexer; a driver circuit coupled to said first transistor, said second transistor, said third transistor and said fourth transistor; and programmable memory coupled to control said first transistor, said second transistor, said third transistor and said fourth transistor in configurations such that a signal from said first input/output line is driven by said driver circuit over said second input/output line, a signal from said second input/output line is driven by said driver circuit over said first input/output line, a signal from said third input line is driven by said driver circuit over said second input/output line, and a signal from said fourth input line is driven by said driver circuit over said first input/output line.
Claim 9
Dependent Claim
57 words
A buffer circuit as described in claim 6 wherein said first multiplexer circuit further comprises a first programmable memory cell for selecting between said first input/output line and said third input line and wherein said second multiplexer circuit further comprises a second programmable memory cell for selecting between said second input/output line and said fourth input line.
Claim 10
Dependent Claim
43 words
A buffer circuit as described in claim 6 wherein programmable memory is also for controlling said first transistor, said second transistor, said third transistor, and said fourth transistor to implement an open circuit between said first input/output line and said second input/output line.
Claim 11
Dependent Claim
52 words
A buffer circuit as described in claim 6 wherein said programmable memory comprises a first memory cell and a second memory cell wherein said first memory cell is coupled to gates of said first and fourth transistors and said second memory cell is coupled to gates of said second and third transistors.
Claim 12
Dependent Claim
20 words
A buffer circuit as described in claim 6 wherein said driver circuit comprises a pair of serially coupled inverter circuits.
Claim 13
Dependent Claim
168 words
A programable integrated circuit having a buffer circuit comprising: a first input/output signal line coupled to a first transistor of a transistor network through a multiplexer, and coupled to a second transistor of said transistor network, said multiplexer controlled by a first programmable memory cell; a second input/output signal coupled to a third and a fourth transistor of said transistor network; a third input line coupled to said first transistor of said transistor network through said multiplexer; a driver circuit coupled to said transistor network; and second and third programable memory cells coupled to control said transistor network in configurations such that a signal from said first input/output line is driven by said driver circuit over said second input/output line in one configuration, a signal from said second input/output line is driven by said driver circuit over said first input/output line in a second configuration, and a signal from said third input line is driven by said driver circuit over said second input/output line in a third configuration.
Claim 14
Dependent Claim
168 words
A programable integrated circuit having a buffer circuit comprising: a first input/output signal line coupled to a first transistor of a transistor network through a multiplexer, and coupled to a second transistor of said transistor network, said multiplexer controlled by a first programmable memory cell; a second input/output signal coupled to a third and a fourth transistor of said transistor network; a third input line coupled to said first transistor of said transistor network through said multiplexer; a driver circuit coupled to said transistor network; and second and third programable memory cells coupled to control said transistor network in configurations such that a signal from said first input/output line is driven by said driver circuit over said second input/output line in one configuration, a signal from said second input/output line is driven by said driver circuit over said first input/output line in a second configuration, and a signal from said third input line is driven by said driver circuit over said second input/output line in a third configuration.
Claim 15
Dependent Claim
70 words
A programable integrated circuit as described in claim 11 wherein said transistor network is for driving said signal from said first input/output line by said driver circuit over said second input/output line provided said multiplexer is configured by said first programmable memory cell to select said first input/output line and provided said second and said third programmable memory cells are programmed with a first state and a second state, respectively.
Claim 16
Dependent Claim
70 words
A programmable integrated circuit as described in claim 12 wherein said transistor network is for driving said signal from said third input line by said driver circuit over said second input/output line provided said multiplexer is configured by said first programmable memory cell to select said third input line and provided said second and said third programmable memory cells are programmed with said first state and said second state, respectively.
Claim 17
Dependent Claim
53 words
A programmable integrated circuit as described in claim 12 wherein said transistor network is for driving said signal from said second input/output line by said driver circuit and over said first input/output line provided said second and said third programmable memory cells are programmed with said second state and said first state, respectively.
Claim 18
Dependent Claim
51 words
A programmable integrated circuit as described in claim 11 wherein said transistor network comprises first, second, third and fourth transistors and wherein said second memory cell is coupled to gates of said first and third transistors and said third memory cell is coupled to gates of said second and fourth transistors.
Claim 19
Dependent Claim
35 words
A programmable integrated circuit as described in claim 15 wherein said driver circuit comprises a pair of serially coupled inverter circuits coupled between said first and second transistors and between said third and fourth transistors.
Claim 20
Dependent Claim
214 words
A programmable integrated circuit having a buffer circuit comprising: a first input/output line coupled to a first transistor of a transistor network through a first multiplexer and coupled to a second transistor of said transistor network, said first multiplexer controlled by a first programmable memory cell; a second input/output line coupled to a third transistor of said transistor network through a second multiplexer and coupled to a fourth transistor of transistor network, said second multiplexer controlled by a second programmable memory cell; a third input line coupled to said first transistor of said transistor network through said first multiplexer; a fourth input line coupled to said third transistor of said transistor network through said second multiplexer; a driver circuit coupled between said transistor network; and third and fourth programmable memory cells coupled to control said transistor network in configurations such that a signal from said first input/output line is driven by said driver circuit over said second input/output line, a signal from said second input/output line is driven by said driver circuit over said first input/output line, a signal from said third input line is driven by said driver circuit over said second input/output line, and a signal from said fourth input line is driven by said driver circuit over said first input/output line.
Claim 21
Dependent Claim
214 words
A programmable integrated circuit having a buffer circuit comprising: a first input/output line coupled to a first transistor of a transistor network through a first multiplexer and coupled to a second transistor of said transistor network, said first multiplexer controlled by a first programmable memory cell; a second input/output line coupled to a third transistor of said transistor network through a second multiplexer and coupled to a fourth transistor of transistor network, said second multiplexer controlled by a second programmable memory cell; a third input line coupled to said first transistor of said transistor network through said first multiplexer; a fourth input line coupled to said third transistor of said transistor network through said second multiplexer; a driver circuit coupled between said transistor network; and third and fourth programmable memory cells coupled to control said transistor network in configurations such that a signal from said first input/output line is driven by said driver circuit over said second input/output line, a signal from said second input/output line is driven by said driver circuit over said first input/output line, a signal from said third input line is driven by said driver circuit over said second input/output line, and a signal from said fourth input line is driven by said driver circuit over said first input/output line.
Claim 22
Dependent Claim
132 words
A programmable integrated circuit as described in claim 17 wherein said transistor network is for driving said signal from said first input/output line by said driver circuit over said second input/output line provided said first multiplexer is configured by said first programmable memory cell to select said first input/output line and provided said third and fourth programmable memory cells are programmed with a first state and a second state, respectively, and wherein said transistor network is for driving said signal from said third input line by said driver circuit over said second input/output line provided said first multiplexer is configured by said first programmable memory cell to select said third input line and provided said third and fourth programmable memory cells are programmed with said first state and said second state, respectively.
Claim 23
Dependent Claim
132 words
A programable integrated circuit as described in claim 17 wherein said transistor network is for driving said signal from said second input/output line by said driver circuit over said first input/output line provided said second multiplexer is configured by said second programmable memory cell to select said second input/output line and provided said third and fourth programmable memory cells are programmed with a second state and a first state, respectively, and wherein said transistor network is for driving said signal from said fourth input line by said driver circuit over said first input/output line provided said second multiplexer is configured by said second programable memory cell to select said fourth input line and provided said third and fourth programmable memory cells are programmed with said second state and said first state, respectively.
Claim 24
Dependent Claim
39 words
A programmable integrated circuit as described in claim 17 wherein said third memory cell is coupled to gates of said first and fourth transistors and said fourth memory cell is coupled to gates of said second and third transistors.
Claim 25
Dependent Claim
37 words
A programmable integrated circuit as described in claim 20 wherein said driver circuit comprises a pair of serially coupled inverter circuits and is coupled between said first and second transistors and between said third and fourth transistors.
Claim 26
Dependent Claim
25 words
A programmable integrated circuit as described in claim 17 wherein one signal is supplied to both said third input line and said fourth input line.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-12-10 | 2000-06-10 | 2000-12-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-12-10 | 2004-06-10 | 2004-12-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-12-10 | 2008-06-10 | 2008-12-10 | $7700.00 | Window Closed / Lapsed |