US5202593A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Bi-directional bus repeater
Assignee: Fairchild Semiconductor Corp
•
Filing: 1991-10-30
•
Granted: 1993-04-13
•
Expires: 2011-10-30
Abstract
Abstract A bi-directional bus repeater includes two unidirectional bus repeaters connected for retransmitting signals in opposite directions between two buses. When an external bus driver pulls either bus low, one of the unidirectional bus repeaters pulls the other bus low. When the external bus driver allows the bus to rise to the high logic level, the unidirectional bus repeater temporarily supplies a high charging current to the other bus to quickly pull it up. Each unidirectional bus repeater also generates signals indicating when it is actively pulling its output bus up or down and the indicating signals inhibit one unidirectional bus repeater from actively driving its output when the other unidirectional bus repeater is actively driving its output.
Inventors
- 👤 Thomas B. Huang
- 👤 Yih-Chyun Jenq
- 👤 Keith Lofstrom
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 21:56
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/01; H03K5/02; H03K5/026
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
135 words
A bi-directional bus repeater for transmitting signals between first and second buses comprising: first unidirectional bus repeater means, connected for receiving a first logic signal carried on said first bus and at least one first indicating signal, for generating a second logic signal on said second bus when said first logic signal is asserted and said first indicating signal is not asserted, and for asserting at least one second indicating signal when generating said second logic signal; and second unidirectional bus repeater means, connected for receiving said second logic signal and said at least one second indicating signal, for generating said first logic signal when said second logic signal is asserted and said second indicating signal is not asserted, and for asserting said at least one first indicating signal when generating said first logic signal.
Claim 2
Dependent Claim
135 words
A bi-directional bus repeater for transmitting signals between first and second buses comprising: first unidirectional bus repeater means, connected for receiving a first logic signal carried on said first bus and at least one first indicating signal, for generating a second logic signal on said second bus when said first logic signal is asserted and said first indicating signal is not asserted, and for asserting at least one second indicating signal when generating said second logic signal; and second unidirectional bus repeater means, connected for receiving said second logic signal and said at least one second indicating signal, for generating said first logic signal when said second logic signal is asserted and said second indicating signal is not asserted, and for asserting said at least one first indicating signal when generating said first logic signal.
Claim 3
Dependent Claim
153 words
The bi-directional bus repeater in accordance with claim 1 wherein said first unidirectional bus repeater means comprises: buffer means, connected for receiving PULL UP and PULL DOWN signals, for driving said second logic signal to a high logic state upon assertion of said PULL UP indicating signal and for driving said second logic signal to a low logic level in response to assertion of said PULL DOWN signal, said PULL UP and PULL DOWN signals comprising said at least one second indicating signal; logic gate means, connected for receiving said first logic signal and said at least one first indicating signal, for asserting and deasserting said PULL DOWN signal in response to logical combinations of states of said first logic signal and said at least one first indicating signal; and single-shot means, connected for receiving said PULL DOWN signal, for temporarily asserting said PULL UP signal when said PULL DOWN signal is deasserted.
Claim 4
Dependent Claim
18 words
The bi-directional bus repeater in accordance with claim 1 wherein said logic gate means comprises a NOR gate.
Claim 5
Dependent Claim
81 words
The bi-directional bus repeater in accordance with claim 2 wherein said buffer means comprises: a source of high logic level, a source of low logic level, a first transistor having load terminals connected between said source of high logic level and said second bus, and a control terminal receiving said PULL UP signal, and a second transistor having load terminals connected between said source of low logic level and said second bus, and a control terminal receiving said PULL DOWN signal.
Claim 6
Dependent Claim
29 words
The bi-directional bus repeater in accordance with claim 4 wherein said buffer means further comprises a resistor connected between said source of high logic level and said second bus.
Claim 7
Dependent Claim
351 words
A bi-directional bus repeater for transmitting signals between first and second buses comprising: first unidirectional bus repeater means, connected for receiving a first logic signal carried on said first bus and at least one first indicating signal, for generating a second logic signal on said second bus when said first logic signal is asserted and said first indicating signal is not asserted, and for asserting at least one second indicating signal when generating said second logic signal; and second unidirectional bus repeater means, connected for receiving said second logic signal and said at least one second indicating signal, for generating said first logic signal when said second logic signal is asserted and said second indicating signal is not asserted, and for asserting said at least one first indicating signal when generating said first logic signal; wherein said first unidirectional bus repeater means comprises: buffer means, connected for receiving PULL UP and PULL DOWN signals, for driving said second logic signal to a high logic state upon assertion of said PULL UP indicating signal and for driving said second logic signal to a low logic level in response to assertion of said PULL DOWN signal, said PULL UP and PULL DOWN signals comprising said at least one second indicating signal; a NOR gate, connected for receiving said first logic signal and said at least one first indicating signal, for asserting and deasserting said PULL DOWN signal in response to logical combinations of states of said first logic signal and said at least one first indicating signal; and single-shot means, connected for receiving said PULL DOWN signal, for temporarily asserting said PULL UP signal when said PULL DOWN signal is deasserted; wherein said buffer means comprises: a source of high logic level, a source of low logic level, a first transistor having load terminals connected between said source of high logic level and said second bus and a control terminal receiving said PULL UP signal, and a second transistor having load terminals connected between said source of low logic level and said second bus and a control terminal receiving said PULL DOWN signal.
Claim 8
Dependent Claim
351 words
A bi-directional bus repeater for transmitting signals between first and second buses comprising: first unidirectional bus repeater means, connected for receiving a first logic signal carried on said first bus and at least one first indicating signal, for generating a second logic signal on said second bus when said first logic signal is asserted and said first indicating signal is not asserted, and for asserting at least one second indicating signal when generating said second logic signal; and second unidirectional bus repeater means, connected for receiving said second logic signal and said at least one second indicating signal, for generating said first logic signal when said second logic signal is asserted and said second indicating signal is not asserted, and for asserting said at least one first indicating signal when generating said first logic signal; wherein said first unidirectional bus repeater means comprises: buffer means, connected for receiving PULL UP and PULL DOWN signals, for driving said second logic signal to a high logic state upon assertion of said PULL UP indicating signal and for driving said second logic signal to a low logic level in response to assertion of said PULL DOWN signal, said PULL UP and PULL DOWN signals comprising said at least one second indicating signal; a NOR gate, connected for receiving said first logic signal and said at least one first indicating signal, for asserting and deasserting said PULL DOWN signal in response to logical combinations of states of said first logic signal and said at least one first indicating signal; and single-shot means, connected for receiving said PULL DOWN signal, for temporarily asserting said PULL UP signal when said PULL DOWN signal is deasserted; wherein said buffer means comprises: a source of high logic level, a source of low logic level, a first transistor having load terminals connected between said source of high logic level and said second bus and a control terminal receiving said PULL UP signal, and a second transistor having load terminals connected between said source of low logic level and said second bus and a control terminal receiving said PULL DOWN signal.
Claim 9
Dependent Claim
29 words
The bi-directional bus repeater in accordance with claim 6 wherein said buffer means further comprises a resistor connected between said source of high logic level and said second bus.
References Cited (Backward Citations)
US4161786A
Cited
US4768188A
Cited
US4604689A
Cited
US4837788A
Cited
US4974153A
Cited
US5036473A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-04-12 | 1996-10-12 | 1997-04-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-04-12 | 2000-10-12 | 2001-04-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-04-12 | 2004-10-12 | 2005-04-13 | $7700.00 | Window Closed / Lapsed |