Patent US3288060A successfully refreshed from Google Patents.
US5627480A
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Tristatable bidirectional buffer for tristate bus lines
Assignee: Xilinx Inc
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Filing: 1996-02-08
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Granted: 1997-05-06
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Expires: 2016-02-08
Abstract
Abstract The direction of a bidirectional buffer inserted along a bus line is dynamically controlled to be always away from the signal source. The signals which select a tristate buffer to turn on for driving the bus also affect or determine the direction of all buffers inserted in the bus line. Since only one tristate enable signal will be active, the direction which each bidirectional buffer should drive is dynamically determined by the presently active enable signal.
Inventors
- 👤 Steven P. Young
- 👤 Trevor J. Bauer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 22:20
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0175; H03K19/0185; H03K19/018592
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
149 words
A bus structure comprising: (a) a bus line; (b) at least one bidirectional buffer separating said bus line into at least two bus line segments; (c) for each said bus line segment, at least one tristate buffer for controllably applying a signal to said bus line segment, said tristate buffer receiving an input signal on a tristate buffer input signal line and an enable signal on a tristate buffer enable signal line, and applying said input signal to said bus line segment in response to an enable signal on said tristate buffer enable signal line; (d) at least one control unit for controlling the direction of said at least one bidirectional buffer, said control unit being controlled by signals from said tristate buffer enable signal lines to direct said bidirectional buffer to carry said signal applied to said bus line segment away from said tristate buffer input signal line.
Claim 2
Dependent Claim
149 words
A bus structure comprising: (a) a bus line; (b) at least one bidirectional buffer separating said bus line into at least two bus line segments; (c) for each said bus line segment, at least one tristate buffer for controllably applying a signal to said bus line segment, said tristate buffer receiving an input signal on a tristate buffer input signal line and an enable signal on a tristate buffer enable signal line, and applying said input signal to said bus line segment in response to an enable signal on said tristate buffer enable signal line; (d) at least one control unit for controlling the direction of said at least one bidirectional buffer, said control unit being controlled by signals from said tristate buffer enable signal lines to direct said bidirectional buffer to carry said signal applied to said bus line segment away from said tristate buffer input signal line.
Claim 3
Dependent Claim
67 words
A bus structure as in claim 1 in which said at least one control unit for controlling the direction of said at least one bidirectional buffer comprises a race contention control unit receiving signals from enable signal line to the left and right, having a structure which places said bidirectional buffer into a high impedance state in response to enable signal line from both left and right.
Claim 4
Dependent Claim
50 words
A bus structure as in claim 1 in which said at least one control unit for controlling the direction of said at least one bidirectional buffer comprises a high impedance control unit which places said bidirectional buffer into a high impedance state in response to a high impedance control signal.
Claim 5
Dependent Claim
70 words
A bus structure as in claim 1 in which said at least one control unit for controlling the direction of said at least one bidirectional buffer is controlled by a plurality of enable signals from a corresponding plurality of enable signal lines; and said at least one control unit comprises at least one logic gate having transistors distributed to tiles in which enable signals for controlling said transistors are generated.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-05-05 | 2000-11-04 | 2001-05-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-05-05 | 2004-11-04 | 2005-05-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-05-05 | 2008-11-04 | 2009-05-06 | $7700.00 | Window Closed / Lapsed |