US5656950A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Interconnect lines including tri-directional buffer circuits
Assignee: Xilinx Inc
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Filing: 1995-10-26
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Granted: 1997-08-12
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Expires: 2015-10-26
Abstract
Abstract A metal interconnect line for conducting a first signal from a first line segment of a field programmable gate array to a second line segment. The metal interconnect line substantially spans across the width of the field programmable gate array and has at least one bi-directional buffer that separates the metal interconnect line into a plurality of independent segments. Each of these segments can conduct signals independently from the other segments when the bidirectional buffer is in a tristate mode. Alternatively, a single signal may be routed through the entire length of the metal line in one or the other direction, and repowered along the way. One or more of the bi-directional buffers are used to actively drive the signal(s) onto later segments of the metal interconnect line.
Inventors
- 👤 Khue Duong
- 👤 Stephen M. Trimberger
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 14:00
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17736; H03K19/0175; H03K19/0185; H03K19/018592; H03K19/17704
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
129 words
A field programmable interconnect structure comprising: a long line; and at least one buffer circuit placed into said long line, thereby dividing said long line into a first input/output conductor and a second input/output conductor, wherein said at least one buffer circuit includes: a first input line; means for selecting between a first signal on said first input/output conductor and a second signal on said first input line: a driver circuit coupled to said first input/output conductor, said means for selecting, and said second input/output conductor; means for enabling said driver circuit to provide an output signal of said means for selecting to said second input/output conductor; and means for enabling said driver circuit to provide a third signal on said second input/output conductor to said first input/output conductor.
Claim 2
Dependent Claim
129 words
A field programmable interconnect structure comprising: a long line; and at least one buffer circuit placed into said long line, thereby dividing said long line into a first input/output conductor and a second input/output conductor, wherein said at least one buffer circuit includes: a first input line; means for selecting between a first signal on said first input/output conductor and a second signal on said first input line: a driver circuit coupled to said first input/output conductor, said means for selecting, and said second input/output conductor; means for enabling said driver circuit to provide an output signal of said means for selecting to said second input/output conductor; and means for enabling said driver circuit to provide a third signal on said second input/output conductor to said first input/output conductor.
Claim 3
Dependent Claim
44 words
A field programmable interconnect structure as in claim 1 further comprising: a plurality of configurable logic blocks; a plurality of interconnect lines; means for connecting said configurable logic blocks to said interconnect lines; and means for connecting said interconnect lines to said long line.
Claim 4
Dependent Claim
16 words
A field programmable interconnect structure as in claim 1 further including a plurality of long lines.
Claim 5
Dependent Claim
32 words
A field programmable interconnect structure as in claim 1 in which said buffer circuit can be placed into a tristate mode, thereby isolating said first and second input/output conductors from each other.
Claim 6
Dependent Claim
30 words
A field programmable interconnect structure as in claim 1 in which said long line is approximately the length of an integrated circuit chip in which said long line is formed.
Claim 7
Dependent Claim
28 words
A field programmable interconnect structure as in claim 2 in which said at least one long line is approximately the length of four of said configurable logic blocks.
Claim 8
Dependent Claim
23 words
A field programmable interconnect structure as in claim 2 in which said long line is divided into four segments by three buffer circuits.
Claim 9
Dependent Claim
47 words
A field programmable interconnect structure as in claim 1 further including: a second input line; and means for choosing between said third signal on said second input/output conductor and a fourth signal on said second input line, said driver circuit further coupled to said means for choosing.
Claim 10
Dependent Claim
34 words
A field programmable interconnect structure as in claim 1 further including a plurality of buffer circuits on said long line, thereby providing a multi-segmented long line, and at least one continuous, uninterrupted long line.
Claim 11
Dependent Claim
87 words
An interconnect device comprising: a first input/output conductor; a second input/output conductor; an input line; a first multiplexer coupled to said first input/output conductor and said input line; a driver circuit coupled to said first input/output conductor, said first multiplexer, and said second input/output conductor; means for enabling said driver circuit to provide an output signal of said first multiplexer to said second input/output conductor; and means for enabling said driver circuit to provide a third signal on said second input/output conductor to said first input/output conductor.
Claim 12
Dependent Claim
87 words
An interconnect device comprising: a first input/output conductor; a second input/output conductor; an input line; a first multiplexer coupled to said first input/output conductor and said input line; a driver circuit coupled to said first input/output conductor, said first multiplexer, and said second input/output conductor; means for enabling said driver circuit to provide an output signal of said first multiplexer to said second input/output conductor; and means for enabling said driver circuit to provide a third signal on said second input/output conductor to said first input/output conductor.
Claim 13
Dependent Claim
36 words
The interconnect structure of claim 10 further including: a second input line; and a second multiplexer coupled to said second input/output conductor and said second input line, said driver circuit further coupled to said second multiplexer.
Claim 14
Dependent Claim
197 words
A field programmable chip comprising: a plurality of configurable logic blocks; a plurality of interconnect lines for interconnecting said configurable logic blocks; a switch matrix coupled to said interconnect lines for electrically conducting a signal from a first interconnect line to a second interconnect line; a plurality of long lines for conducting signals thereupon; at least one programmable buffer circuit provided at an intermediate point on one of said long lines, thereby dividing said long line into a first input/output conductor and a second input/output conductor, wherein said at least one buffer circuit includes: a first input line; means for selecting between a first signal on said first input/output conductor and a second signal on said first input line; a driver circuit coupled to said first input/output conductor, said means for selecting, and said second input/output conductor; means for enabling said driver circuit to provide an output signal of said means for selecting to said second input/output conductor; and means for enabling said driver circuit to provide a third signal on said second input/output conductor to said first input/output conductor; and a programmable device for connecting at least one long line to at least one interconnect line.
Claim 15
Dependent Claim
197 words
A field programmable chip comprising: a plurality of configurable logic blocks; a plurality of interconnect lines for interconnecting said configurable logic blocks; a switch matrix coupled to said interconnect lines for electrically conducting a signal from a first interconnect line to a second interconnect line; a plurality of long lines for conducting signals thereupon; at least one programmable buffer circuit provided at an intermediate point on one of said long lines, thereby dividing said long line into a first input/output conductor and a second input/output conductor, wherein said at least one buffer circuit includes: a first input line; means for selecting between a first signal on said first input/output conductor and a second signal on said first input line; a driver circuit coupled to said first input/output conductor, said means for selecting, and said second input/output conductor; means for enabling said driver circuit to provide an output signal of said means for selecting to said second input/output conductor; and means for enabling said driver circuit to provide a third signal on said second input/output conductor to said first input/output conductor; and a programmable device for connecting at least one long line to at least one interconnect line.
Claim 16
Dependent Claim
44 words
The interconnect structure of claim 12 further including: a second input line; and means for choosing between a third signal on said second input/output conductor and a fourth signal on said second input line, said driver circuit further coupled to said means for choosing.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-08-11 | 2001-02-10 | 2001-08-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-08-11 | 2005-02-10 | 2005-08-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-08-11 | 2009-02-10 | 2009-08-12 | $7700.00 | Window Closed / Lapsed |