Method and apparatus for processing pipelined memory commands

Claim 2

A memory device command generator to receive command packets indicative of a memory command, a row address and a column address, the command generator comprising: a plurality of command units, each of the command units being enabled upon receipt of an acknowledgment signal, each of the command units, when enabled, operable to store a plurality of command bits of a command packet received by the command units and to output at least one command signal corresponding to the command bits; and a command processor coupled to each of the command units, the command processor operable to receive at least one of the command signals output from an enabled command unit, to generate the acknowledgment signal in response to one of the command signals, and to process the command signals by generating at least one control signal responsive thereto.

Claim 3

The memory device command generator of claim 1 , further comprising a command unit selector coupled to each of the command units, the command unit selector operable to determine which of the command units are available to store command bits, and to enable one of the available command units to store a plurality of command bits.

Claim 4

The command generator of claim 1 wherein each of the command units comprise: a counter operable to count in one direction from a first count to a second count responsive to a clock signal, the counting being initiated responsive to a start signal derived from a timing signal associated with the command packet received by a command unit when the command unit is enabled; and a start command generator generating a start command signal at one of a plurality of respective counts of the counter that are a function of the nature of the command indicated by the stored command bits, the start command signal causing the command processor coupled to each of the command units to process the command bits to generate the control signal and the acknowledgment signal.

Claim 5

The command generator of claim 3 wherein the counts at which the start command generator generates the start command signal is further a function of a clock speed signal indicative of the frequency of the clock signal.

Claim 6

The command generator of claim 3 wherein the count at which the start command signal is generated is intermediate the first and second counts.

Claim 7

The command generator of claim 1 wherein each of the command units comprise: a counter counting in one direction from an initial count to a terminal count responsive to a clock signal, the counting being initiated responsive to a start signal derived from a timing signal associated with the command packet received by a command unit when the command unit is enabled; and a start command generator generating a start command signal at one of a plurality of respective counts of the counter that are a function of a clock speed signal indicative of the frequency of the clock signal, the start command signal causing the command processor coupled to each of the command units to process the bits to generate the control signal and the acknowledgment signal.

Claim 8

The command generator of claim 6 wherein the counter tenninates counting responsive to a count halt signal.

Claim 9

The command generator of claim 6 wherein the count at which the start command signal is generated is intermediate the initial count and the terminal count.

Claim 10

The command generator of claim 1 wherein the plurality of command units are coupled to the command processor through a common bus shared by all of the command units.

Claim 11

The command generator of claim 1 wherein each of the command units is operable to generate a respective start command signal to cause the command processor to process the bits received from the command unit to generate the control signal, each of the command units operable to generate the start command signal until receipt of the acknowledgment signal, and wherein the command processor is operable to generate the acknowledgment signal responsive to receipt of the start command signal and to couple the acknowledgment signal to the command unit from which it received the start command signal.

Claim 12

The command generator of claim 1 wherein the command processor initiates processing of the command bits responsive to a start command signal, and wherein each of the command units comprise: a counter operable to count in one direction from a first count to a second count responsive to a clock signal, the counting being initiated responsive to a start signal derived from a timing signal associated with the command packet received by a command unit when the command unit is enabled; a counter preloader coupled to the counter and operable to load the counter with a value of the initial count that corresponds to the timing of the command packet as received at a predetermined location in the command generator; a plurality of counter decoders coupled the counter to receive the count of the counter, the counter decoders each operable to generate the start command signal responsive to decoding respective values of the count, the value decoded by each decoder being a function of at least one of the clock speed and the nature of the command indicated by the command bits applied to the command unit; and a latch receiving the command bits applied to the command unit, the latch operable to store the command bits in the command unit responsive to the start command signal.

Claim 13

A memory device command generator receiving command packets indicative of a memory command, a row address and a command address, the command generator comprising: a command buffer operable to receive and to store at least a portion of at least one packet word in each command packet, the command buffer operable to apply the stored portion of each command packet to a command bus; a plurality of command units coupled to the command bus of the command buffer, each of the command units operable to be enabled upon receipt of an acknowledgment signal and, when enabled, operable to store a plurality of command bits of at least one packet word and to output the command bits stored in the command unit to an output bus, and operable to generate a respective busy signal indicating that the command unit is storing command bits and has not output the stored command bits to the output bus, each of the command units comprising; a counter operable to count in one direction from a first count to a second count responsive to a clock signal, the counting being initiated responsive to a start signal derived from a timing signal associated with the command packet received by an enabled command unit; and a start command generator operable to generate a start command signal at one of a plurality of respective counts of the counter that are a function of a clock speed signal indicative of the frequency of the clock signal; a control circuit operable to receive the busy signals from the respective command units to determine which of the command units are storing a portion of a packet word, the control circuit operable to apply a respective select signal to one of the command units from which a busy signal is not being received to cause the command unit receiving the select signal to store the portion of the packet word received from the command buffer; and a command processor coupled to the output bus of the command units to receive the command bits and coupled to the command units to receive the start command signals, the command processor operable to generate a command signal responsive to a clock signal, the clock speed signal, and the nature of the memory operation, and operable to generate the acknowledgment signal responsive to receiving one of the start command signals.

Claim 14

A memory device command generator receiving command packets indicative of a memory command, a row address and a command address, the command generator comprising: a command buffer operable to receive and to store at least a portion of at least one packet word in each command packet, the command buffer operable to apply the stored portion of each command packet to a command bus; a plurality of command units coupled to the command bus of the command buffer, each of the command units operable to be enabled upon receipt of an acknowledgment signal and, when enabled, operable to store a plurality of command bits of at least one packet word and to output the command bits stored in the command unit to an output bus, and operable to generate a respective busy signal indicating that the command unit is storing command bits and has not output the stored command bits to the output bus, each of the command units comprising; a counter operable to count in one direction from a first count to a second count responsive to a clock signal, the counting being initiated responsive to a start signal derived from a timing signal associated with the command packet received by an enabled command unit; and a start command generator operable to generate a start command signal at one of a plurality of respective counts of the counter that are a function of a clock speed signal indicative of the frequency of the clock signal; a control circuit operable to receive the busy signals from the respective command units to determine which of the command units are storing a portion of a packet word, the control circuit operable to apply a respective select signal to one of the command units from which a busy signal is not being received to cause the command unit receiving the select signal to store the portion of the packet word received from the command buffer; and a command processor coupled to the output bus of the command units to receive the command bits and coupled to the command units to receive the start command signals, the command processor operable to generate a command signal responsive to a clock signal, the clock speed signal, and the nature of the memory operation, and operable to generate the acknowledgment signal responsive to receiving one of the start command signals.

Claim 15

The command generator of claim 12 wherein the counter terminates counting responsive to a count halt signal, and wherein each of the command units is operable to generate the count halt signal in response to receiving the acknowledgment signal.

Claim 16

The command generator of claim 12 wherein the count at which the start command signal is generated is intermediate the first and second counts.

Claim 17

A packetized dynamic random access memory, comprising: a clock generator circuit operable to generate an internal clock signal having a phase relative to an external clock signal determined by a phase command signal; at least one array of memory cells operable to store data at a location determined by a row address and a column address; a row address circuit operable to receive and decode the row address, and to select a row of memory cells corresponding to the row address responsive to a first set of command signals; a column address circuit operable to receive or apply data to one of the memory cells in the selected row corresponding to the column address responsive to a second set of command signals; a data path circuit operable to couple data between an external terminal and the column address circuit responsive to a third set of command signals; and a command generator operable to receive command packets indicative of a command, a row address and a command address, the command generator comprising: a plurality of command units, each of the command units being enabled upon receipt of an acknowledgment signal, each of the command units, when enabled, operable to store a plurality of command bits of a command packet received by the command units and to output at least one command signal corresponding to the command bits; and a command processor coupled to each of the command units, the command processor operable to receive at least one of the command signals output from an enabled command unit, to generate the acknowledgment signal in response to one of the command signals, and to process the command signals by generating at least one control signal responsive thereto.

Claim 18

A packetized dynamic random access memory, comprising: a clock generator circuit operable to generate an internal clock signal having a phase relative to an external clock signal determined by a phase command signal; at least one array of memory cells operable to store data at a location determined by a row address and a column address; a row address circuit operable to receive and decode the row address, and to select a row of memory cells corresponding to the row address responsive to a first set of command signals; a column address circuit operable to receive or apply data to one of the memory cells in the selected row corresponding to the column address responsive to a second set of command signals; a data path circuit operable to couple data between an external terminal and the column address circuit responsive to a third set of command signals; and a command generator operable to receive command packets indicative of a command, a row address and a command address, the command generator comprising: a plurality of command units, each of the command units being enabled upon receipt of an acknowledgment signal, each of the command units, when enabled, operable to store a plurality of command bits of a command packet received by the command units and to output at least one command signal corresponding to the command bits; and a command processor coupled to each of the command units, the command processor operable to receive at least one of the command signals output from an enabled command unit, to generate the acknowledgment signal in response to one of the command signals, and to process the command signals by generating at least one control signal responsive thereto.

Claim 19

The packetized dynamic random access memory of claim 15 , further comprising a command unit selector coupled to each of the command units, the command unit selector operable to determine which of the command units are available to store command bits, and to enable one of the available command units to store a plurality of command bits, the command unit selector further operable to activate one of the command units.

Claim 20

The packetized dynamic random access memory of claim 15 wherein each of the command units comprise: a counter operable to count in one direction from a first count to a second count responsive to a clock signal, the counting being initiated responsive to a start signal derived from a timing signal associated with the command packet received by a command unit when the command unit is enabled; and a start command generator oenerating a start command signal at one of a plurality of respective counts of the counter that are a function of the nature of the command indicated by the stored command bits, the start command signal causing the command processor coupled to each of the command units to process the command bits to generate the control signal and the acknowledgment signal.

Claim 21

The packetized dynamic random access memory of claim 17 wherein the counts at which the start command generator generates the start command signal is further a function of a clock speed signal indicative of the frequency of the clock signal.

Claim 22

The packetized dynamic random access memory of claim 17 wherein the count at which the start command signal is generated is intermediate the first and second counts.

Claim 23

The packetized dynamic random access memory of claim 15 wherein each of the command units comprise: a counter counting in one direction from an initial count to a terminal count responsive to a clock signal, the counting being initiated responsive to a start signal derived from a timing signal associated with the command packet received by a command unit when the command unit is enabled; and a start command generator generating a start command signal at one of a plurality of respective counts of the counter that are a function of a clock speed signal indicative of the frequency of the clock signal, the start command signal causing the command processor coupled to each of the command units to process the bits to generate the control signal and the acknowledgment signal.

Claim 24

The packetized dynamic random access memory of claim 20 wherein the counter terminates counting responsive to a count halt signal.

Claim 25

The packetized dynamic random access memory of claim 20 wherein the count at which the start command signal is generated is intermediate the initial count and the terminal count.

Claim 26

The packetized dynamic random access memory of claim 15 wherein the plurality of command units are coupled to the command processor through a common bus shared by all of the command units.

Claim 27

The packetized dynamic random access memory of claim 15 wherein each of the command units is operable to generate a respective start command signal to cause the command processor to process the bits received from the command unit to generate the control signal, each of the command units operable to generate the start command signal until receipt of the acknowledgment signal, and wherein the command processor is operable to generate the acknowledgment signal responsive to receipt of the start command signal and to couple the acknowledgment signal to the command unit from which it received the start command signal.

Claim 28

The packetized dynamic random access memory of claim 15 wherein the command processor initiates processing of the command bits responsive to a start command signal, and wherein each of the command units comprise: a counter operable to count in one direction from a first count to a second count responsive to a clock signal, the counting being initiated responsive to a start signal derived from a timing signal associated with the command packet received by a command unit when the command unit is enabled; a counter preloader coupled to the counter and operable to load the counter with a value of the initial count that corresponds to the timing of the command packet as received at a predetermined location in the command generator; a plurality of counter decoders coupled the counter to receive the count of the counter, the counter decoders each operable to generate the start command signal responsive to decoding respective values of the count, the value decoded by each decoder being a function of at least one of the clock speed and the nature of the command indicated by the command bits applied to the command unit; and a latch receiving the command bits applied to the command unit, the latch operable to store the command bits in the command unit responsive to the start command signal.

Claim 29

A computer system, comprising: a processor having a processor bus; an input device coupled to the processor through the processor bus to allow data to be entered into the computer system; an output device coupled to the processor through the processor bus to allow data to be output from the computer system; and a packetized dynamic random access memory coupled to the processor bus to allow data to be stored, to receive a plurality of input signals and generate a plurality of output signals on respective, externally accessible terminals, the packetized dynamic random access memory comprising: a clock generator circuit generating an internal clock signal having a phase relative to an external clock signal determined by a phase command signal; at least one array of memory cells to store data at a location determined by a row address and a column address; a row address circuit to receive and decode the row address, and select a row of memory cells corresponding to the row address responsive to a first set of command signals; a column address circuit to receive or apply data to one of the memory cells in the selected row corresponding to the column address responsive to a second set of command signals; a data path circuit to couple data between an external terminal and the column address circuit responsive to a third set of command signals; and a command generator receiving command packets indicative of a command, a row address and a command address, the command generator comprising: a plurality of command units, each of the command units being enabled upon receipt of an acknowledgment signal, each of the command units, when enabled, operable to store a plurality of command bits of a command packet received by the command units and to output at least one command signal corresponding to the command bits; and a command processor coupled to each of the command units, the command processor operable to receive at least one of the command signals output from an enabled command unit, to generate the acknowledgment signal in response to one of the command signals, and to process the command signals by generating at least one control signal responsive thereto.

Claim 30

A computer system, comprising: a processor having a processor bus; an input device coupled to the processor through the processor bus to allow data to be entered into the computer system; an output device coupled to the processor through the processor bus to allow data to be output from the computer system; and a packetized dynamic random access memory coupled to the processor bus to allow data to be stored, to receive a plurality of input signals and generate a plurality of output signals on respective, externally accessible terminals, the packetized dynamic random access memory comprising: a clock generator circuit generating an internal clock signal having a phase relative to an external clock signal determined by a phase command signal; at least one array of memory cells to store data at a location determined by a row address and a column address; a row address circuit to receive and decode the row address, and select a row of memory cells corresponding to the row address responsive to a first set of command signals; a column address circuit to receive or apply data to one of the memory cells in the selected row corresponding to the column address responsive to a second set of command signals; a data path circuit to couple data between an external terminal and the column address circuit responsive to a third set of command signals; and a command generator receiving command packets indicative of a command, a row address and a command address, the command generator comprising: a plurality of command units, each of the command units being enabled upon receipt of an acknowledgment signal, each of the command units, when enabled, operable to store a plurality of command bits of a command packet received by the command units and to output at least one command signal corresponding to the command bits; and a command processor coupled to each of the command units, the command processor operable to receive at least one of the command signals output from an enabled command unit, to generate the acknowledgment signal in response to one of the command signals, and to process the command signals by generating at least one control signal responsive thereto.

Claim 31

The computer system of claim 26 , further comprising a command unit selector coupled to each of the command units, the command unit selector operable to determine which of the command units are available to store command bits, and to enable one of the available command units to store a plurality of command bits.

Claim 32

The computer system of claim 26 wherein each of the command units comprise: a counter operable to count in one direction from a first count to a second count responsive to a clock signal, the counting being initiated responsive to a start signal derived from a timing signal associated with the command packet received by a command unit when the command unit is enabled; and a start command generator generating a start command signal at one of a plurality of respective counts of the counter that are a function of the nature of the command indicated by the stored command bits, the start command signal causing the command processor coupled to each of the command units to process the command bits to generate the control signal and the acknowledgment signal.

Claim 33

The computer system of claim 28 wherein the counts at which the start command generator generates the start command signal is further a function of a clock speed signal indicative of the frequency of the clock signal.

Claim 34

The computer system of claim 28 wherein the count at which the start command signal is generated is intermediate the first and second counts.

Claim 35

The computer system of claim 26 wherein each of the command units comprise: a counter counting in one direction from an initial count to a terminal count responsive to a clock signal, the counting being initiated responsive to a start signal derived from a timing signal associated with the command packet received by a command unit when the command unit is enabled; and a start command generator generating a start command signal at one of a plurality of respective counts of the counter that are a function of a clock speed signal indicative of the frequency of the clock signal, the start command signal causing the command processor coupled to each of the command units to process the bits to generate the control signal and the acknowledgment signal.

Claim 36

The computer system of claim 31 wherein the counter terminates counting responsive to a count halt signal.

Claim 37

The computer system of claim 31 wherein the count at which the start command signal is generated is intermediate the initial count and the terminal count.

Claim 38

The computer system of claim 26 wherein the plurality of command units are coupled to the command processor through a common bus shared by all of the command units.

Claim 39

The computer system of claim 26 wherein each of the command units is operable to generate a respective start command signal to cause the command processor to process the bits received from the command unit to generate the control signal, each of the command units operable to generate the start command signal until receipt of the acknowledgment signal, and wherein the command processor is operable to generate the acknowledgment signal responsive to receipt of the start command signal and to couple the acknowledgment signal to the command unit from which it received the start command signal.

Claim 40

The computer system of claim 26 wherein the command processor initiates processing of the command bits responsive to a start command signal, and wherein each of the command units comprise: a counter operable to count in one direction from a first count to a second count responsive to a clock signal, the counting being initiated responsive to a start signal derived from a timing signal associated with the command packet received by a command unit when the command unit is enabled; a counter preloader coupled to the counter and operable to load the counter with a value of the initial count that corresponds to the timing of the command packet as received at a predetermined location in the command generator; a plurality of counter decoders coupled the counter to receive the count of the counter, the counter decoders each operable to gencrate the start command signal responsive to decoding respective values of the count, the value decoded by each decoder being a function of at least one of the clock speed and the nature of the command indicated by the command bits applied to the command unit; and a latch receiving the command bits applied to the command unit, the latch operable to store the command bits in the command unit responsive to the start command signal.