US5887146A — Symmetric multiprocessing computer with non-unifo…

Claim 1

Independent Claim 280 words

A scalable multiprocessor computer system, comprising: a backplane, including at least one backplane communication bus; a plurality of motherboards, detachably connected to said backplane; each motherboard interfacing to said at least one backplane communication bus, each of said plurality of motherboards including: at least one backplane communication bus interface mechanism interfacing at least one of said plurality of motherboards to said at least one backplane communication bus; a motherboard communication bus comprising a first segment that is selectably interfaceable to said at least one backplane communication bus and at least one second segment, said motherboard communication bus including a crossbar register switch selectably interconnecting said at least one second segment of said motherboard communication bus to said first segment; a motherboard communication bus request arbitration mechanism arbitrating requests from said plurality of motherboards for access to said first segment and said at least one second segment of said motherboard communication bus by selected ones of said plurality of motherboards; a memory system including main memory distributed among said plurality of motherboards, directory memory for maintaining main memory coherency with caches on other motherboards, and a memory controller module for accessing said main memory and directory memory and interfacing to said motherboard communication bus; and at least one daughterboard, detachably connected to said motherboard and interfacing to said motherboard communication bus, said at least one daughterboard further including: a motherboard communication bus interface module, for interfacing said at least one daughterboard to said motherboard communication bus and a local bus on said daughterboard; and at least one cache memory system including cache memory and a cache controller module maintaining said cache memory for a processor of said scalable multiprocessor computer system.

Claim 2

Dependent Claim 280 words

A scalable multiprocessor computer system, comprising: a backplane, including at least one backplane communication bus; a plurality of motherboards, detachably connected to said backplane; each motherboard interfacing to said at least one backplane communication bus, each of said plurality of motherboards including: at least one backplane communication bus interface mechanism interfacing at least one of said plurality of motherboards to said at least one backplane communication bus; a motherboard communication bus comprising a first segment that is selectably interfaceable to said at least one backplane communication bus and at least one second segment, said motherboard communication bus including a crossbar register switch selectably interconnecting said at least one second segment of said motherboard communication bus to said first segment; a motherboard communication bus request arbitration mechanism arbitrating requests from said plurality of motherboards for access to said first segment and said at least one second segment of said motherboard communication bus by selected ones of said plurality of motherboards; a memory system including main memory distributed among said plurality of motherboards, directory memory for maintaining main memory coherency with caches on other motherboards, and a memory controller module for accessing said main memory and directory memory and interfacing to said motherboard communication bus; and at least one daughterboard, detachably connected to said motherboard and interfacing to said motherboard communication bus, said at least one daughterboard further including: a motherboard communication bus interface module, for interfacing said at least one daughterboard to said motherboard communication bus and a local bus on said daughterboard; and at least one cache memory system including cache memory and a cache controller module maintaining said cache memory for a processor of said scalable multiprocessor computer system.

Claim 3

Dependent Claim 20 words

The scalable multiprocessor computer system of claim 1 wherein said main memory is contiguously addressable across said plurality of motherboards.

Claim 4

Dependent Claim 30 words

The scalable multiprocessor computer system of claim 1 wherein said backplane includes four backplane communication busses, and each of said plurality of motherboards includes four backplane communication bus interface modules.

Claim 5

Dependent Claim 26 words

The scalable multiprocessor computer system of claim 1 wherein one of said plurality of motherboards is selected to provide a system clock signal for all motherboards.

Claim 6

Dependent Claim 29 words

The scalable multiprocessor computer system of claim 4 wherein a second one of said plurality of motherboards is selected to provide a backup system clock signal for all motherboards.

Claim 7

Dependent Claim 37 words

The scalable multiprocessor computer system of claim 1 wherein each of said plurality of motherboards includes a peripheral interface module, said peripheral interface module interfacing to said motherboard communication bus, and to at least one peripheral device.

Claim 8

Dependent Claim 36 words

The scalable multiprocessor computer system of claim 6 wherein said at least one peripheral device is one of a local area network (LAN) device, a small computer system interface (SCSI) device or an expansion card device.

Claim 9

Dependent Claim 18 words

The scalable multiprocessor computer system of claim 1 wherein said at least one daughterboard includes two processor modules.

Claim 10

Dependent Claim 32 words

The scalable multiprocessor computer system of claim 8 wherein said at least one cache memory system on said on said at least one daughterboard provides a cache for said two processor modules.

Claim 11

Dependent Claim 284 words

A scalable distributed memory multiprocessor computer system including a backplane comprising a plurality of identical independent backplane buses, said backplane providing communication paths for a plurality of motherboards, each of said motherboards including at least one processor with a local cache memory, a motherboard communications bus, a motherboard communications bus to backplane interface module, and a memory system, wherein: said motherboard communications bus to backplane interface module includes three input queues of high, medium, and low priority, and packets sent on said backplane to a motherboard are placed in one of said input queues depending on the priority of each packet; all packets to the same cache line use the same one of said plurality of identical independent backplane buses; high priority packets are always accepted into said memory system on a motherboard without needing to retry; medium priority packets received from said plurality of identical independent backplane buses are granted onto a motherboard communication bus in the order in which said medium priority packages are received from said plurality of identical independent backplane buses; packets for cache-inhibited reads, cache-inhibited writes, and cache-inhibited write unlocks are ordered with previous invalidate command and read invalidate reply packets previously inserted in said medium priority input queue; packets to be received by more than one motherboard will arrive to each motherboard simultaneously; all copyback invalidate commands and copyback commands are sent out on said backplane to a receiving motherboard; all invalidate copybacks are sent out on said backplane to a receiving motherboard; and a motherboard will retry any local resource requests while said medium input queue of said motherboard communications bus to backplane interface module contains any read invalidate reply, invalidate command, or copyback invalidate command packets.

Claim 12

Dependent Claim 284 words

A scalable distributed memory multiprocessor computer system including a backplane comprising a plurality of identical independent backplane buses, said backplane providing communication paths for a plurality of motherboards, each of said motherboards including at least one processor with a local cache memory, a motherboard communications bus, a motherboard communications bus to backplane interface module, and a memory system, wherein: said motherboard communications bus to backplane interface module includes three input queues of high, medium, and low priority, and packets sent on said backplane to a motherboard are placed in one of said input queues depending on the priority of each packet; all packets to the same cache line use the same one of said plurality of identical independent backplane buses; high priority packets are always accepted into said memory system on a motherboard without needing to retry; medium priority packets received from said plurality of identical independent backplane buses are granted onto a motherboard communication bus in the order in which said medium priority packages are received from said plurality of identical independent backplane buses; packets for cache-inhibited reads, cache-inhibited writes, and cache-inhibited write unlocks are ordered with previous invalidate command and read invalidate reply packets previously inserted in said medium priority input queue; packets to be received by more than one motherboard will arrive to each motherboard simultaneously; all copyback invalidate commands and copyback commands are sent out on said backplane to a receiving motherboard; all invalidate copybacks are sent out on said backplane to a receiving motherboard; and a motherboard will retry any local resource requests while said medium input queue of said motherboard communications bus to backplane interface module contains any read invalidate reply, invalidate command, or copyback invalidate command packets.

Claim 13

Dependent Claim 53 words

The scalable distributed memory multiprocessor computer system of claim 10, wherein: packets of low priority include cache-inhibited reads, cache inhibited writes, cache-inhibited write unlock and write-through; packets of medium priority include invalidate commands, read invalidate replies, and copyback invalidate commands; and packets of high priority include copyback replies, copyback invalidate replies, and writebacks.

Claim 14

Dependent Claim 279 words

A scalable multiprocessor computer system, comprising: a backplane, including at least one backplane communication bus; a plurality of motherboards, detachably connected to said backplane; each motherboard interfacing to said at least one backplane communication bus, each of said plurality of motherboards including: at least one backplane communication bus interface mechanism interfacing at least one of said plurality of motherboards to said at least one backplane communication bus; a motherboard communication bus comprising a first segment that is selectably interfaceable to said at least one backplane communication bus and a plurality of second segments, said motherboard communication bus including means for selectably interconnecting one of said plurality of second segments of said motherboard communication bus to said first segment; an arbitration means for arbitrating requests from said plurality of motherboards for access to said first segment and said one of said plurality of second segments of said motherboard communication bus by selected ones of said plurality of motherboards; a memory system including main memory distributed among said plurality of motherboards, directory means for maintaining main memory coherency with caches on other motherboards, and a memory controller means for accessing said main memory and directory memory and interfacing to said motherboard communication bus; and at least one daughterboard, detachably connected to said motherboard and interfacing to said motherboard communication bus, said at least one daughterboard further including: a motherboard communication bus interface means for interfacing said at least one daughterboard to said motherboard communication bus and a local bus on said daughterboard; and at least one cache memory system including cache memory and a cache controller means for maintaining said cache memory for a processor of said scalable multiprocessor computer system.

Claim 15

Dependent Claim 279 words

A scalable multiprocessor computer system, comprising: a backplane, including at least one backplane communication bus; a plurality of motherboards, detachably connected to said backplane; each motherboard interfacing to said at least one backplane communication bus, each of said plurality of motherboards including: at least one backplane communication bus interface mechanism interfacing at least one of said plurality of motherboards to said at least one backplane communication bus; a motherboard communication bus comprising a first segment that is selectably interfaceable to said at least one backplane communication bus and a plurality of second segments, said motherboard communication bus including means for selectably interconnecting one of said plurality of second segments of said motherboard communication bus to said first segment; an arbitration means for arbitrating requests from said plurality of motherboards for access to said first segment and said one of said plurality of second segments of said motherboard communication bus by selected ones of said plurality of motherboards; a memory system including main memory distributed among said plurality of motherboards, directory means for maintaining main memory coherency with caches on other motherboards, and a memory controller means for accessing said main memory and directory memory and interfacing to said motherboard communication bus; and at least one daughterboard, detachably connected to said motherboard and interfacing to said motherboard communication bus, said at least one daughterboard further including: a motherboard communication bus interface means for interfacing said at least one daughterboard to said motherboard communication bus and a local bus on said daughterboard; and at least one cache memory system including cache memory and a cache controller means for maintaining said cache memory for a processor of said scalable multiprocessor computer system.

Claim 16

Dependent Claim 184 words

A crossbar register switch for use in a scaleable multiprocessor computer system including at least one backplane communication bus, and a plurality of motherboards interfaced to said at least one backplane communication bus, each of said plurality of motherboards including a motherboard communication bus comprising a first segment that is selectably interfaceable to said at least one backplane communication bus and a plurality of second segments; said crossbar register switch comprising: an interface to said first segment of said motherboard communication bus; a plurality of bidirectional ports, said bidirectional ports interfacing to said plurality of second segments of said motherboard communication bus; a motherboard communication bus request arbitration mechanism arbitrating requests from said plurality of motherboards for access to said first segment and to one of said plurality of second segments of said motherboard communication bus by selected ones of said plurality of motherboards; wherein said crossbar register switch selectably interconnects said first segment of said motherboard communication bus to one of said second segments of said motherboard communication bus through a bidirectional port based arbitration by said motherboard communication bus request arbitration mechanism.

Claim 17

Dependent Claim 184 words

A crossbar register switch for use in a scaleable multiprocessor computer system including at least one backplane communication bus, and a plurality of motherboards interfaced to said at least one backplane communication bus, each of said plurality of motherboards including a motherboard communication bus comprising a first segment that is selectably interfaceable to said at least one backplane communication bus and a plurality of second segments; said crossbar register switch comprising: an interface to said first segment of said motherboard communication bus; a plurality of bidirectional ports, said bidirectional ports interfacing to said plurality of second segments of said motherboard communication bus; a motherboard communication bus request arbitration mechanism arbitrating requests from said plurality of motherboards for access to said first segment and to one of said plurality of second segments of said motherboard communication bus by selected ones of said plurality of motherboards; wherein said crossbar register switch selectably interconnects said first segment of said motherboard communication bus to one of said second segments of said motherboard communication bus through a bidirectional port based arbitration by said motherboard communication bus request arbitration mechanism.

Claim 18

Dependent Claim 58 words

The crossbar register switch of claim 13 wherein said scaleable multiprocessor computer system includes a memory system including main memory distributed among said plurality of motherboards, directory memory for maintaining main memory coherency with caches on other motherboards, and a memory controller module for accessing said main memory and directory memory and interfacing to said motherboard communication bus.

Claim 19

Dependent Claim 22 words

The crossbar register switch of claim 13 wherein said crossbar register switch is implemented in a plurality of identical integrated circuit modules.

Claim 20

Dependent Claim 207 words

In a scalable distributed memory multiprocessor computer system including a backplane comprising a plurality of identical independent backplane buses, said backplane providing communication paths for a plurality of motherboards, each of said motherboards including at least one processor with a local cache memory, a motherboard communications bus, a motherboard communications bus to backplane interface module, and a memory system; a method for communicating between said motherboard communication bus and said backplane busses comprising: providing three input queues of high, medium, and low priority; designating which input queue to place a packet sent on said backplane to a motherboard; guaranteeing that high priority packets will be received at the destination; allowing packets to be received by more than one motherboard to arrive to each motherboard simultaneously; ordering packets in said medium priority queue so that any medium priority packets which involve snoops or invalidations are ordered with previous invalidate command and read invalidate reply packets previously inserted in said medium priority queue across all backplane busses; and sending any local memory requests out onto one of said backplane busses and into said while said medium priority queue of said motherboard communications bus to backplane interface module contains any read invalidate reply, invalidate command, or copyback invalidate command packets.

Claim 21

Dependent Claim 207 words

In a scalable distributed memory multiprocessor computer system including a backplane comprising a plurality of identical independent backplane buses, said backplane providing communication paths for a plurality of motherboards, each of said motherboards including at least one processor with a local cache memory, a motherboard communications bus, a motherboard communications bus to backplane interface module, and a memory system; a method for communicating between said motherboard communication bus and said backplane busses comprising: providing three input queues of high, medium, and low priority; designating which input queue to place a packet sent on said backplane to a motherboard; guaranteeing that high priority packets will be received at the destination; allowing packets to be received by more than one motherboard to arrive to each motherboard simultaneously; ordering packets in said medium priority queue so that any medium priority packets which involve snoops or invalidations are ordered with previous invalidate command and read invalidate reply packets previously inserted in said medium priority queue across all backplane busses; and sending any local memory requests out onto one of said backplane busses and into said while said medium priority queue of said motherboard communications bus to backplane interface module contains any read invalidate reply, invalidate command, or copyback invalidate command packets.

Claim 22

Dependent Claim 40 words

The method of claim 16, further including the steps of: designating packets of low priority to include requests; designating packets of medium priority to include replies and snoops; and designating packets of high priority to include copyback replies and writebacks.

Claim 23

Dependent Claim 58 words

The method of claim 16, further including the steps of: designating packets of low priority to include cache-inhibited reads, cache inhibited writes, cache-inhibited write unlock and write-through; designating packets of medium priority to include invalidate commands, read invalidate replies, and copyback invalidate commands; and designating packets of high priority to include copyback replies, copyback invalidate replies, and writebacks.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	2002-03-22	2002-09-21	2003-03-23	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2006-03-22	2006-09-21	2007-03-23	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2010-03-22	2010-09-21	2011-03-23	$7700.00	Window Closed / Lapsed

Symmetric multiprocessing computer with non-uniform memory access architecture

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