Fast, dual ported cache controller for data processors in a packet switched cache coherent multiprocessor system

Claim 2

A cache memory controller for controlling access to a cache memory array for storing a set of data blocks, said cache memory controller comprising: two ports for receiving access requests, including a first port for receiving access requests from a first device and a second port for receiving access requests from a second device distinct from said first device; all said access requests from said first device and from said second device including an address value, said access requests from said second device further including a mode flag; each address value including a first set of most significant address bits, and a second set of cache index address bits; a hit/miss signal generator for processing said address value in each access request so as to generate a hit/miss signal indicating whether a data block corresponding to said address value is stored in said cache memory device; and access circuitry having two modes of operation, including a first standard mode of operation in which read/write access to said cache memory array is preceded by generation of said hit/miss signal by said hit/miss signal generator in response to said access request's address value, and a second accelerated mode of operation in which operation of said hit/miss signal generator is suppressed and read/write access to said cache memory array is initiated without waiting for said hit/miss signal generator to process said access request's address value; wherein said access circuitry uses said first mode of operation for all access requests by said first device and for access requests by said second device when said mode flag has a first value, and uses said second mode of operation for access requests by said second device when said mode flag has a second value distinct from said first value.

Claim 3

A cache memory device, comprising: a cache line array having 2 N cache lines for storing 2 N data blocks; a cache tag array having 2 N cache tags, each cache tag denoting a cache line state value and an address tag for a corresponding one of said 2 N cache lines; a cache controller for controlling access to said cache memory device, said cache controller having two ports for receiving access requests, including a first port for receiving access requests from a first device and a second port for receiving access requests from a second device distinct from said first device; all said access requests from said first device and from said second device including an address value, said access requests from said second device further including a mode flag; each address value including a first set of most significant address bits, and a second set of cache index address bits; said cache controller further including: a comparator for comparing said first set of address bits in each access request's address value with the address tag stored in the one of said cache tags corresponding to said cache index address bits in said each access request's address value and generating a hit/miss signal indicating whether said first set of address bits match said address tag; and access circuitry having two modes of operation, including a first standard mode of operation in which read/write access to said cache line array and write access to said cache tag array is preceded by generation of said hit/miss signal by said comparator in response to said access request's address value, and a second accelerated mode of operation in which read/write access to said cache line array and write access to said cache tag array are initiated without waiting for said comparator to process said access request's address value; wherein said access circuitry uses said first mode of operation for all access requests by said first device and for access requests by said second device when said mode flag has a first value, and uses said second mode of operation for access requests by said second device when said mode flag has a second value distinct from said first value.

Claim 4

A cache memory device, comprising: a cache line array having 2 N cache lines for storing 2 N data blocks; a cache tag array having 2 N cache tags, each cache tag denoting a cache line state value and an address tag for a corresponding one of said 2 N cache lines; a cache controller for controlling access to said cache memory device, said cache controller having two ports for receiving access requests, including a first port for receiving access requests from a first device and a second port for receiving access requests from a second device distinct from said first device; all said access requests from said first device and from said second device including an address value, said access requests from said second device further including a mode flag; each address value including a first set of most significant address bits, and a second set of cache index address bits; said cache controller further including: a comparator for comparing said first set of address bits in each access request's address value with the address tag stored in the one of said cache tags corresponding to said cache index address bits in said each access request's address value and generating a hit/miss signal indicating whether said first set of address bits match said address tag; and access circuitry having two modes of operation, including a first standard mode of operation in which read/write access to said cache line array and write access to said cache tag array is preceded by generation of said hit/miss signal by said comparator in response to said access request's address value, and a second accelerated mode of operation in which read/write access to said cache line array and write access to said cache tag array are initiated without waiting for said comparator to process said access request's address value; wherein said access circuitry uses said first mode of operation for all access requests by said first device and for access requests by said second device when said mode flag has a first value, and uses said second mode of operation for access requests by said second device when said mode flag has a second value distinct from said first value.

Claim 5

A cache memory controller for controlling access to a cache memory array for storing a set of data blocks, said cache memory controller comprising: at least one port for receiving access requests, all of said access requests including an address value, each address value including a first set of most significant address bits, and a second set of cache index address bits; at least a subset of said access requests further including a mode flag; a hit/miss signal generator for processing said address value in each access request so as to generate a hit/miss signal indicating whether a data block corresponding to said address value is stored in said cache memory device; and access circuitry having two modes of operation, including a first standard mode of operation in which read/write access to said cache memory array is preceded by generation of said hit/miss signal by said hit/miss signal generator in response to said access request's address value, and a second accelerated mode of operation in which operation of said hit/miss signal generator is suppressed and read/write access to said cache memory array is initiated without waiting for said hit/miss signal generator to process said access request's address value; wherein said access circuitry uses said first mode of operation for any access requests that do not include said mode flag as well as for access requests having said mode flag set to a first value, and uses said second mode of operation for access requests having said mode flag set to a second value distinct from said first value.

Claim 6

A cache memory controller for controlling access to a cache memory array for storing a set of data blocks, said cache memory controller comprising: at least one port for receiving access requests, all of said access requests including an address value, each address value including a first set of most significant address bits, and a second set of cache index address bits; at least a subset of said access requests further including a mode flag; a hit/miss signal generator for processing said address value in each access request so as to generate a hit/miss signal indicating whether a data block corresponding to said address value is stored in said cache memory device; and access circuitry having two modes of operation, including a first standard mode of operation in which read/write access to said cache memory array is preceded by generation of said hit/miss signal by said hit/miss signal generator in response to said access request's address value, and a second accelerated mode of operation in which operation of said hit/miss signal generator is suppressed and read/write access to said cache memory array is initiated without waiting for said hit/miss signal generator to process said access request's address value; wherein said access circuitry uses said first mode of operation for any access requests that do not include said mode flag as well as for access requests having said mode flag set to a first value, and uses said second mode of operation for access requests having said mode flag set to a second value distinct from said first value.

Claim 7

The cache memory controller of claim 3, wherein said cache memory array includes: a cache line array having 2 N cache lines for storing 2 N data blocks; and a cache tag array having 2 N cache tags, each cache tag denoting a cache line state value and an address tag for a corresponding one of said 2 N cache lines; said hit/miss signal generator including a comparator for comparing said first set of address bits in each access request's address value with the address tag stored in the one of said cache tags corresponding to said cache index address bits in said each access request's address value and generating said hit/miss signal so as to indicate whether said first set of address bits match said address tag.

Claim 10

The method of claim 5, including storing 2 N cache tags in a cache tag array, each cache tag denoting a cache line state value and an address tag for a corresponding one of 2 N cache lines in said cache memory array; and said address value processing step including comparing said first set of address bits in each access request's address value with the address tag stored in the one of said cache tags corresponding to said cache index address bits in said each access request's address value and generating said hit/miss signal so as to indicate whether said first set of address bits match said address tag.

Claim 11

The method of claim 5, said receiving step including receiving at a first port access requests from a first device and receiving at a second port access requests from a second device distinct from said first device, wherein only said access requests from said second device include said mode flag; wherein said method provides accelerated cache memory access only to access requests from said second device for which said mode flag is equal to said second value.