US5388224A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Processor identification mechanism for a multiprocessor system
Assignee: Hewlett Packard Development Co LP
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Filing: 1992-04-24
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Granted: 1995-02-07
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Expires: 2012-04-24
Abstract
Abstract A computer system including a plurality of processors and a bus coupling the processors to one another via respective bus interfaces. The bus includes a plurality of slots for coupling the interfaces to the bus. Each interface includes an ID register coupled to the interface device, the ID register containing identification information unique to the slot of the bus used to couple the respective interface to the bus. The interface device is responsive to an address command cycle of the bus to place the identification information from the ID register on the bus during a READ bus transaction initiated by the interface and directed to another slot of the bus. A processor requiring identification of the corresponding slot causes the respective interface to initiate a READ bus transaction directed to another slot of the bus. The bus is operated so that the module at the slot to which the READ transaction is directed, returns the slot identification information to the initiator interface for communication to the corresponding processor.
Inventors
- 👤 Barry A. Maskas
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 03:00
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/36; G06F13/368; G06F13/374; G06F13/38; G06F13/42; G06F13/4204; G06F13/4208; G06F13/4217
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
248 words
A method for a processor to identify a corresponding slot in a multiprocessor system, the multiprocessor system including a bus having a plurality of slots to couple modules to the bus, preselected ones of the slots each being used to couple processor modules to the bus, each processor module including a processor coupled to an interface, the interface being coupled to the bus, the method comprising the steps of: for each of the preselected ones of the slots, providing an ID register for storing identification information unique to the corresponding slot; coupling each ID register to the interface of the corresponding processor module; performing a command address cycle on the bus, the command address cycle requiring an interface to place the identification information from the corresponding ID register on the bus during a READ bus transaction initiated by the interface and directed to another module coupled to the bus; causing an interface coupled to a processor requiring identification of the slot by which it is coupled to the bus to initiate a READ bus transaction directed to another module coupled to the bus; latching, at the module to which the READ transaction is directed, the identification information placed on the bus by the initiator interface during the command address cycle and returning the identification information to the initiator interface, over the bus as a data item; and operating the interface to pass the identification information as a data item to the corresponding processor to identify the corresponding slot.
Claim 2
Independent Claim
248 words
A method for a processor to identify a corresponding slot in a multiprocessor system, the multiprocessor system including a bus having a plurality of slots to couple modules to the bus, preselected ones of the slots each being used to couple processor modules to the bus, each processor module including a processor coupled to an interface, the interface being coupled to the bus, the method comprising the steps of: for each of the preselected ones of the slots, providing an ID register for storing identification information unique to the corresponding slot; coupling each ID register to the interface of the corresponding processor module; performing a command address cycle on the bus, the command address cycle requiring an interface to place the identification information from the corresponding ID register on the bus during a READ bus transaction initiated by the interface and directed to another module coupled to the bus; causing an interface coupled to a processor requiring identification of the slot by which it is coupled to the bus to initiate a READ bus transaction directed to another module coupled to the bus; latching, at the module to which the READ transaction is directed, the identification information placed on the bus by the initiator interface during the command address cycle and returning the identification information to the initiator interface, over the bus as a data item; and operating the interface to pass the identification information as a data item to the corresponding processor to identify the corresponding slot.
Claim 3
Dependent Claim
189 words
An interface for coupling a processor to a bus via a slot, the interface comprising: an interface device adapted for coupling to the bus; an ID register coupled to the interface device, the ID register containing identification information unique to the slot by which the processor is coupled to the bus; the interface device being responsive to command address cycle of the bus to place the identification information from the ID register on the bus during a READ bus transaction initiated by the interface and directed to another module coupled to the bus so that a processor requiring identification of the slot by which it is coupled to the bus causes the respective interface to initiate a READ bus transaction directed to another module coupled to the bus; the interface further including: means, responsive to a command address cycle on the bus during a READ bus transaction initiated by another interface, for reading the slot identification information from the bus, and for latching the slot identification information; and means for placing the latched slot identification information onto the bus as a data item for return to the other interface.
Claim 4
Dependent Claim
189 words
An interface for coupling a processor to a bus via a slot, the interface comprising: an interface device adapted for coupling to the bus; an ID register coupled to the interface device, the ID register containing identification information unique to the slot by which the processor is coupled to the bus; the interface device being responsive to command address cycle of the bus to place the identification information from the ID register on the bus during a READ bus transaction initiated by the interface and directed to another module coupled to the bus so that a processor requiring identification of the slot by which it is coupled to the bus causes the respective interface to initiate a READ bus transaction directed to another module coupled to the bus; the interface further including: means, responsive to a command address cycle on the bus during a READ bus transaction initiated by another interface, for reading the slot identification information from the bus, and for latching the slot identification information; and means for placing the latched slot identification information onto the bus as a data item for return to the other interface.
Claim 5
Dependent Claim
67 words
An interface for coupling a module to a bus, the interface comprising: means, responsive to a command address cycle on the bus during a READ bus transaction, for reading slot identification information from the bus, and for latching the slot identification information; and means for placing the latched slot identification information onto the bus as a data item during a data cycle following the command address cycle.
Claim 6
Dependent Claim
67 words
An interface for coupling a module to a bus, the interface comprising: means, responsive to a command address cycle on the bus during a READ bus transaction, for reading slot identification information from the bus, and for latching the slot identification information; and means for placing the latched slot identification information onto the bus as a data item during a data cycle following the command address cycle.
Claim 7
Dependent Claim
218 words
A computer system, comprising a plurality of processors; each processor including an interface: a bus coupling the processors to one another via the respective interfaces; the bus including a plurality of slots for coupling the interfaces to the bus; each interface including an ID register coupled to the interface device, the ID register containing identification information unique to the slot of the bus used to couple the respective interface to the bus; the interface device being responsive to a command address cycle of the bus to place the identification information from the ID register on the bus during a READ bus transaction initiated by the interface and directed to another slot of the bus so that a processor requiring identification of the slot by which it is coupled to the bus causes the respective interface to initiate a READ bus transaction directed to another slot of the bus; each interface further including: means, responsive to the command address cycle on the bus during a READ bus transaction initiated by another interface, for reading the slot identification information from the bus, and for latching the slot identification information; and means for placing the latched slot identification information onto the bus as a data item during a data cycle following the command address cycle for return to the initiator interface.
Claim 8
Dependent Claim
218 words
A computer system, comprising a plurality of processors; each processor including an interface: a bus coupling the processors to one another via the respective interfaces; the bus including a plurality of slots for coupling the interfaces to the bus; each interface including an ID register coupled to the interface device, the ID register containing identification information unique to the slot of the bus used to couple the respective interface to the bus; the interface device being responsive to a command address cycle of the bus to place the identification information from the ID register on the bus during a READ bus transaction initiated by the interface and directed to another slot of the bus so that a processor requiring identification of the slot by which it is coupled to the bus causes the respective interface to initiate a READ bus transaction directed to another slot of the bus; each interface further including: means, responsive to the command address cycle on the bus during a READ bus transaction initiated by another interface, for reading the slot identification information from the bus, and for latching the slot identification information; and means for placing the latched slot identification information onto the bus as a data item during a data cycle following the command address cycle for return to the initiator interface.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-02-06 | 1998-08-08 | 1999-02-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-02-06 | 2002-08-08 | 2003-02-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-02-06 | 2006-08-08 | 2007-02-07 | $7700.00 | Window Closed / Lapsed |