EP0735487A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

A fast, dual ported cache controller for data processors in a packet switched cache coherent multiprocessor system

Assignee: Sun Microsystems Inc

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Filing: 1996-03-28

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Granted: —

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Expires: 2016-03-28

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Abstract

Abstract A multiprocessor computer system has data processors and a main memory coupled to a system controller. Each data processor has a cache memory. Each cache memory has a cache controller with two ports for receiving access requests. A first port receives access requests from the associated data processor and a second port receives access requests from the system controller. All cache memory access requests include an address value; access requests from the system controller also include a mode flag. A comparator in the cache controller processes the address value in each access request and generates a hit/miss signal indicating whether the data block corresponding to the address value is stored in the cache memory. The cache controller has two modes of operation, including a first standard mode of operation in which read/write access to the cache memory is preceded by generation of the hit/miss signal by the comparator, and a second accelerated mode of operation in which read/write access to the cache memory is initiated without waiting for the comparator to process the access request's address value. The first mode of operation is used for all access requests by the data processor and for system controller access requests when the mode flag has a first value. The second mode of operation is used for the system controller access requests when the mode flag has a second value distinct from the first value.

Inventors

👤 Zahir Ebrahim
👤 Kevin Normoyle
👤 Satyanarayana Nishtala
👤 William C. Van Loo

Bibliographic Details

Application Number —

Jurisdiction EP

Data Source google_patents

Last Synchronized 2026-10-29 17:58

CPC Classifications

G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0806; G06F12/0815; G06F12/0804; G06F12/0817; G06F12/0831; G06F12/0833

Claims Analysis

Total Claims: 2

Claim 1

Independent Claim 293 words

A cache memory controller for controlling access to a cache memory array for storing a set of data blocks, said cache memory controller comprising: two ports for receiving access requests, including a first port for receiving access requests from a first device and a second port for receiving access requests from a second device distinct from said first device; all said access requests from said first device and from said second device including an address value, said access requests from said second device further including a mode flag; each address value including a first set of most significant address bits, and a second set of cache index address bits; a hit/miss signal generator for processing said address value in each access request so as to generate a hit/miss signal indicating whether a data block corresponding to said address value is stored in said cache memory device; and access circuitry having two modes of operation, including a first standard mode of operation in which read/write access to said cache memory array is preceded by generation of said hit/miss signal by said hit/miss signal generator in response to said access request's address value, and a second accelerated mode of operation in which operation of said hit/miss signal generator is suppressed and read/write access to said cache memory array is initiated without waiting for said hit/miss signal generator to process said access request's address value; wherein said access circuitry uses said first mode of operation for all access requests by said first device and for access requests by said second device when said mode flag has a first value, and uses said second mode of operation for access requests by said second device when said mode flag has a second value distinct from said first value.

Claim 2

Dependent Claim 366 words

A cache memory device, comprising: a cache line array having 2 N cache lines for storing 2 N data blocks; a cache tag array having 2 N cache tags, each cache tag denoting a cache line state value and an address tag for a corresponding one of said 2 N cache lines; a cache controller for controlling access to said cache memory device, said cache controller having two ports for receiving access requests, including a first port for receiving access requests from a first device and a second port for receiving access requests from a second device distinct from said first device; all said access requests from said first device and from said second device including an address value, said access requests from said second device further including a mode flag; each address value including a first set of most significant address bits, and a second set of cache index address bits; said cache controller further including: a comparator for comparing said first set of address bits in each access request's address value with the address tag stored in the one of said cache tags corresponding to said cache index address bits in said each access request's address value and generating a hit/miss signal indicating whether said first set of address bits match said address tag; and access circuitry having two modes of operation, including a first standard mode of operation in which read/write access to said cache line array and write access to said cache tag array is preceded by generation of said hit/miss signal by said comparator in response to said access request's address value, and a second accelerated mode of operation in which read/write access to said cache line array and write access to said cache tag array are initiated without waiting for said comparator to process said access request's address value; wherein said access circuitry uses said first mode of operation for all access requests by said first device and for access requests by said second device when said mode flag has a first value, and uses said second mode of operation for access requests by said second device when said mode flag has a second value distinct from said first value.

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