EP0468480A2
Expired / Lapsed
EP
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Synchronous burst-access memory and word-line driving circuit therefor
Assignee: Oki Electric Industry Co Ltd
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Filing: 1991-07-24
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Granted: —
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Expires: 2011-07-24
Abstract
Abstract A synchronous burst-access memory latches a row address strobe signal, a column address strobe signal, and address signals in synchronization with a clock signal. Data are stored in rows and columns in a memory cell array. Data in a selected row are input and output in serial bursts in synchronization with the clock signal, starting from a selected column. The row and initial column address are provided as external inputs; subsequent column addresses are generated by an internal address counting circuit. A word-line driving circuit for a synchronous memory uses transparent latches to latch the row address strobe signal and address signals, enabling row address decoding to be completed prior to synchronization with the clock signal.
Inventors
- 👤 Atsushi C/O Oki Electric Ind. Co. Ltd. Takasugi
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 08:11
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C7/00; G11C7/10; G11C7/1015; G11C7/1018; G11C7/1072; G11C8/00; G11C8/18
Claims Analysis
Total Claims: 30
Claim 1
Independent Claim
263 words
A synchronous burst-access memory to receive a clock signal, a row address strobe signal, a column address strobe signal, and address signals, comprising: a memory cell array for storing data in memory cells disposed in intersecting rows and columns; latching means for latching the row address strobe signal, the column address strobe signal, and the address signals in synchronization with the clock signal, and for generating first and second internal control signals from the latched signals; input/output means, coupled to said latching means, for external input and output of data in synchronization with said clock signal; row address decoding means, coupled to said memory cell array, for decoding said address signals and selecting a row of memory cells in said memory cell array in response to the first internal control signal; address counting means, preset to a value determined by said address signals in response to the second internal control signal, for counting said clock signal and generating a consecutive series of column addresses starting from the preset value; column address decoding means coupled to said address counting means, for decoding said series of column addresses and selecting corresponding columns in said memory cell array; and data transfer means coupled to said memory cell array, said input/output means, and said address counting means, for transferring data from said input/output means to said memory cell array and from said memory cell array to said input/output means, data being transferred to and from memory cells disposed in columns selected by said column address decoding means in the row selected by said row address decoding means.
Claim 2
Dependent Claim
263 words
A synchronous burst-access memory to receive a clock signal, a row address strobe signal, a column address strobe signal, and address signals, comprising: a memory cell array for storing data in memory cells disposed in intersecting rows and columns; latching means for latching the row address strobe signal, the column address strobe signal, and the address signals in synchronization with the clock signal, and for generating first and second internal control signals from the latched signals; input/output means, coupled to said latching means, for external input and output of data in synchronization with said clock signal; row address decoding means, coupled to said memory cell array, for decoding said address signals and selecting a row of memory cells in said memory cell array in response to the first internal control signal; address counting means, preset to a value determined by said address signals in response to the second internal control signal, for counting said clock signal and generating a consecutive series of column addresses starting from the preset value; column address decoding means coupled to said address counting means, for decoding said series of column addresses and selecting corresponding columns in said memory cell array; and data transfer means coupled to said memory cell array, said input/output means, and said address counting means, for transferring data from said input/output means to said memory cell array and from said memory cell array to said input/output means, data being transferred to and from memory cells disposed in columns selected by said column address decoding means in the row selected by said row address decoding means.
Claim 3
Dependent Claim
23 words
The memory of claim 1, wherein said first internal control signal is generated from said row address strobe signal and said clock signal.
Claim 4
Dependent Claim
23 words
The memory of claim 1, wherein said second internal control signal is generated from said column address strobe signal and said clock signal.
Claim 5
Dependent Claim
13 words
The memory of claim 1, wherein said memory cells are dynamic memory cells.
Claim 6
Dependent Claim
34 words
The memory of claim 1, also comprising frequency-dividing means for dividing said clock signal in frequency before said clock signal is supplied to said latching means, said address counting means, and said input/output means.
Claim 7
Dependent Claim
25 words
The memory of claim 5, wherein said frequency-dividing means divides the frequency of said clock signal by an amount selected by an external control signal.
Claim 8
Dependent Claim
24 words
The memory of claim 5, wherein said frequency-dividing means divides the frequency of said clock signal by an amount selected by a manufacturing option.
Claim 9
Dependent Claim
39 words
The memory of claim 1, also comprising clock control means coupled to said latching means, for blocking input of said clock signal to said address counting means and said input/output means while said column address strobe signal is inactive.
Claim 10
Dependent Claim
26 words
The memory of claim 8, wherein said clock control means comprises an OR gate having said clock signal and said column address strobe signal as inputs.
Claim 11
Dependent Claim
32 words
The memory of claim 8, wherein said latching means generates a third internal control signal causing said input/output means to cease input and output when said column address strobe signal is inactive.
Claim 12
Dependent Claim
66 words
The memory of claim 1, also comprising access counting means, coupled to said address counting means and said input/output means, for counting said clock signal and generating a fourth internal control signal when a certain number of clock signals have been counted, said fourth internal control signal commanding said address counting means to cease generating column addresses and said input/output means to cease input and output.
Claim 13
Dependent Claim
14 words
The memory of claim 11, wherein said number is determined by said address signals.
Claim 14
Dependent Claim
43 words
The memory of claim 12, wherein said access counting means receives said number from said latching means in synchronization with said clock signal when said column address strobe signal becomes active for a second time after said row address strobe signal becomes active.
Claim 15
Dependent Claim
31 words
The memory of claim 12, wherein said access counting means comprises a down-counter preset according to said number, for generating said fourth internal control signal when a certain count is reached.
Claim 16
Dependent Claim
67 words
The memory of claim 12, wherein said access clock counting means comprises: an up-counter for counting said clock signal, thus generating a count value; a register for storing said number; and a match-detecting circuit coupled to said counter and said register, for comparing said count value with contents of said register and generating said fourth control signal when said count value matches said contents of said register.
Claim 17
Dependent Claim
50 words
The memory of claim 13, further comprising disabling means coupled to said latching means, for enabling said access counting means to receive said number from said latching means only during a certain interval after said column address strobe signal first becomes active following activation of said row address strobe signal.
Claim 18
Dependent Claim
17 words
The memory of claim 16, wherein said disabling means determines said interval by counting said clock signal.
Claim 19
Dependent Claim
47 words
The memory of claim 16, further comprising clock control means coupled to said latching means, for blocking input of said clock signal to said address counting means and said input/output means when said column address strobe signal is inactive before and after but not during said interval.
Claim 20
Dependent Claim
25 words
The memory of claim 11, also comprising flag output means coupled to said access counting means, for generating a flag signal indicating completion of access.
Claim 21
Dependent Claim
23 words
The memory of claim 19, wherein said flag signal is generated when said access counting means has counted said number of clock signals.
Claim 22
Dependent Claim
26 words
The memory of claim 19, wherein said flag signal is generated a certain time before said access counting means has counted said number of clock signals.
Claim 23
Dependent Claim
27 words
The memory of claim 19, wherein said flag output means has flag shifting means for delaying output of said flag signal by a selectable amount of time.
Claim 24
Dependent Claim
16 words
The memory of claim 22, wherein said amount of time is selected by a manufacturing option.
Claim 25
Dependent Claim
18 words
The memory of claim 22, wherein said amount of time is selected by an external shift control signal.
Claim 26
Dependent Claim
139 words
The memory of claim 24, wherein said access clock counting means generates an ending signal a certain time before said number of clock signals have been counted, and said flag shifting means comprises: a first tri-state buffer for receiving said ending signal from said access clock counting means and outputting same in response to said shift control signal; a delay line for receiving said ending signal from said access clock counting means and generating a delayed ending signal; a second tri-state buffer coupled to said delay line, for receiving said delayed ending signal from said delay line and outputting same in response to said shift control signal; and an inverter coupled to said first tri-state buffer and said second tri-state buffer, for inverting said shift control signal at a point between said first tri-state buffer and said second-tri-state buffer.
Claim 27
Dependent Claim
226 words
A word-line driving circuit to drive word lines in a synchronous dynamic memory that receives a clock signal, a row address strobe signal, and address signals, comprising: a clock generating circuit for generating an address latch clock signal that becomes active when the row address strobe signal and the clock signal are both active, and remains active until said row address strobe signal becomes inactive; a first transparent latch circuit, clocked by said clock signal, for latching said row address strobe signal and generating therefrom a first internal signal; a second transparent latch circuit, coupled to said clock generating circuit and clocked by said address latch clock signal, for latching the address signals; an address generating circuit, coupled to said second transparent latch circuit, for gen erating a row address from output of said second transparent latch circuit; a word-line decoding circuit coupled to said address generating circuit, for decoding said row address, thus selecting one word line, and generating a second internal signal that becomes active when said word line has been selected; and gating and driving means coupled to said first transparent latch circuit and said word-line decoding circuit, for receiving a control signal, gating said first internal signal according to said second internal signal and said control signal to generate a drive signal, and driving the selected word line by said drive signal.
Claim 28
Dependent Claim
226 words
A word-line driving circuit to drive word lines in a synchronous dynamic memory that receives a clock signal, a row address strobe signal, and address signals, comprising: a clock generating circuit for generating an address latch clock signal that becomes active when the row address strobe signal and the clock signal are both active, and remains active until said row address strobe signal becomes inactive; a first transparent latch circuit, clocked by said clock signal, for latching said row address strobe signal and generating therefrom a first internal signal; a second transparent latch circuit, coupled to said clock generating circuit and clocked by said address latch clock signal, for latching the address signals; an address generating circuit, coupled to said second transparent latch circuit, for gen erating a row address from output of said second transparent latch circuit; a word-line decoding circuit coupled to said address generating circuit, for decoding said row address, thus selecting one word line, and generating a second internal signal that becomes active when said word line has been selected; and gating and driving means coupled to said first transparent latch circuit and said word-line decoding circuit, for receiving a control signal, gating said first internal signal according to said second internal signal and said control signal to generate a drive signal, and driving the selected word line by said drive signal.
Claim 29
Dependent Claim
17 words
The circuit of claim 26, wherein said address latch clock signal is used as said control signal.
Claim 30
Dependent Claim
53 words
The circuit of claim 26, wherein said gating and driving means comprises: a three-input AND gate having said first input signal, said second input signal, and said control signal as inputs; and a word-line driver coupled to said three-input AND gate, for generating said drive signal from output of said three-input AND gate.
References Cited (Backward Citations)
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