US5920510A
Expired / Lapsed
US
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Semiconductor device capable of holding signals independent of the pulse width of an external clock and a computer system including the semiconductor device
Assignee: Renesas Electronics Corp
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Filing: 1997-09-19
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Granted: 1999-07-06
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Expires: 2017-09-19
Abstract
Abstract A semiconductor device and a computer system, incorporating the same, is capable of capturing an external signal at a high speed and stably operating independent of the duty ratio of a clock signal. An external signal ADD is captured into an address latch 22 by a level latch. The level latch is controlled to a through state at the timing in which the external signal is decided and controlled to a latched state in the decision period of the external signal. A pulse generation circuit controls the timing for switching a latch to the through state to a desired timing by a pulse generation circuit 30 in a chip. According to the above structure, the capture of the external signal ADD can be accelerated because the capture of the signal is determined by the setup timing. Moreover, because a latching period is controlled by the pulse generation circuit in the chip, operations are performed in a stable manner without having to depend upon the pulse width of an external clock CLK.
Inventors
- 👤 Seigou Yukutake
- 👤 Takashi Akioka
- 👤 Kinya Mitsumoto
- 👤 Takahiro Nagano
- 👤 Hideo Maejima
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 00:52
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1072; G11C7/22; G11C8/00; G11C8/06
Claims Analysis
Total Claims: 43
Claim 1
Independent Claim
86 words
A semiconductor device, operating synchronously with an external clock signal and having means for holding a signal input from an external unit, and comprising a holding-period control signal generation circuit for generating a holding-period control signal for controlling an input-signal holding period independently of a pulse width of an external clock signal, and both of a start timing and an end timing of said input signal holding period are determined by one of a rising portion and a falling portion of said external clock signal independently.
Claim 2
Dependent Claim
86 words
A semiconductor device, operating synchronously with an external clock signal and having means for holding a signal input from an external unit, and comprising a holding-period control signal generation circuit for generating a holding-period control signal for controlling an input-signal holding period independently of a pulse width of an external clock signal, and both of a start timing and an end timing of said input signal holding period are determined by one of a rising portion and a falling portion of said external clock signal independently.
Claim 3
Dependent Claim
81 words
A semiconductor device, operating synchronously with an external clock signal and having means for holding a signal output from an internal unit, and comprising a holding-period control signal generation circuit for generating a holding-period control signal for controlling an output-signal holding period independently of a pulse width of an external clock signal, and a start timing and an end timing of said input signal holding period are determined by a same rising or falling portion of said external clock signal independently.
Claim 4
Dependent Claim
81 words
A semiconductor device, operating synchronously with an external clock signal and having means for holding a signal output from an internal unit, and comprising a holding-period control signal generation circuit for generating a holding-period control signal for controlling an output-signal holding period independently of a pulse width of an external clock signal, and a start timing and an end timing of said input signal holding period are determined by a same rising or falling portion of said external clock signal independently.
Claim 5
Dependent Claim
44 words
The semiconductor device according to claim 1, wherein the holding-period control signal is a signal that is a result of taking a logical sum of an external clock signal and a one-shot pulse signal generated from a leading edge of the external clock signal.
Claim 6
Dependent Claim
44 words
The semiconductor device according to claim 2, wherein the holding-period control signal is a signal that is a result of taking a logical sum of an external clock signal and a one-shot pulse signal generated from a leading edge of the external clock signal.
Claim 7
Dependent Claim
27 words
The semiconductor device according to claim 1, wherein the holding-period control signal is a one-shot pulse signal generated from the leading edge of an external clock signal.
Claim 8
Dependent Claim
27 words
The semiconductor device according to claim 2, wherein the holding-period control signal is a one-shot pulse signal generated from the leading edge of an external clock signal.
Claim 9
Dependent Claim
21 words
The semiconductor device according to claim 1, wherein the holding-period control signal is a signal generated from a phase-locked loop (PLL).
Claim 10
Dependent Claim
21 words
The semiconductor device according to claim 1, wherein the holding-period control signal is a signal generated from a delay-locked loop (DLL).
Claim 11
Dependent Claim
21 words
The semiconductor device according to claim 1, wherein the holding period can be selected by a program circuit or fuse circuit.
Claim 12
Dependent Claim
32 words
The semiconductor device according to claim 1, wherein a delay circuit having a current switch of an ECL is included as at least one component of the holding-period control signal generation circuit.
Claim 13
Dependent Claim
34 words
The semiconductor device according to claim 1, wherein the holding-period control signal generation circuit includes a delay circuit having a gate circuit driven by a constant current as at least one of its components.
Claim 14
Dependent Claim
73 words
A semiconductor device operating synchronously with an external clock signal and having means for holding a signal input from an external unit, wherein the means for holding a signal input from an external unit includes a two-stage holding means of a master latch and a slave latch and a control timing of the slave latch occurs at least 10% of an operation cycle time earlier than a control timing of the master latch.
Claim 15
Dependent Claim
73 words
A semiconductor device operating synchronously with an external clock signal and having means for holding a signal input from an external unit, wherein the means for holding a signal input from an external unit includes a two-stage holding means of a master latch and a slave latch and a control timing of the slave latch occurs at least 10% of an operation cycle time earlier than a control timing of the master latch.
Claim 16
Dependent Claim
78 words
A semiconductor device according to claim 12, further comprising: a delay locked loop which receives an external clock signal and outputs the control timing of the slave latch; and a delay circuit connected between the delay locked loop and the master latch, the delay circuit providing a delay amount that is selected so that the control timing of the master latch is approximately centered in a period in which the signal input from an external unit is valid.
Claim 17
Dependent Claim
180 words
A synchronous random access memory (SRAM) device for capturing an external signal in an accelerated fashion and for holding the external signal for a time sufficient to accurately carry out a read/write process using the external signal, the SRAM device comprising: a first terminal for receiving the external signal; latch means for capturing the external signal; a second terminal for receiving a clock signal having a duty cycle; and means for modifying the clock signal and applying the modified clock signal to the latch means; wherein a timing of a rising (or falling) edge of said modified clock signal is determined by a timing of a rising (or falling) edge of said clock signal, a timing of a falling (or rising) edge of said modified clock signal is determined by a timing of a rising (or falling) edge of said clock signal, and wherein the latch means is controlled by the modified clock signal so that the external signal is held by the latch means for a predetermined period of time independent of the duty cycle of the clock signal.
Claim 18
Dependent Claim
180 words
A synchronous random access memory (SRAM) device for capturing an external signal in an accelerated fashion and for holding the external signal for a time sufficient to accurately carry out a read/write process using the external signal, the SRAM device comprising: a first terminal for receiving the external signal; latch means for capturing the external signal; a second terminal for receiving a clock signal having a duty cycle; and means for modifying the clock signal and applying the modified clock signal to the latch means; wherein a timing of a rising (or falling) edge of said modified clock signal is determined by a timing of a rising (or falling) edge of said clock signal, a timing of a falling (or rising) edge of said modified clock signal is determined by a timing of a rising (or falling) edge of said clock signal, and wherein the latch means is controlled by the modified clock signal so that the external signal is held by the latch means for a predetermined period of time independent of the duty cycle of the clock signal.
Claim 19
Dependent Claim
15 words
The SRAM device according to claim 14, wherein the external signal is an address signal.
Claim 20
Dependent Claim
20 words
The SRAM device according to claim 14, wherein the means for modifying the clock signal includes a pulse generation circuit.
Claim 21
Dependent Claim
20 words
The SRAM device according to claim 14, wherein the means for modifying the clock signal includes a phase locked loop.
Claim 22
Dependent Claim
20 words
The SRAM device according to claim 14, wherein the means for modifying the clock signal includes a delay locked loop.
Claim 23
Dependent Claim
20 words
The SRAM device according to claim 14, wherein the means for modifying the clock signal includes a synchronous mirror delay.
Claim 24
Dependent Claim
117 words
A circuit comprising: a latch which receives an input signal; and a pulse generation circuit which receives a clock signal and outputs a modified clock signal to the latch, and; wherein a timing of a rising (or falling) edge of said modified clock signal is determined by a timing of a rising (or falling) edge of said clock signal, a timing of a falling (or rising) edge of said modified clock signal is determined by a timing of a rising (or falling) edge of said clock signal, and wherein the latch holds the input signal for a predetermined period of time as determined by the modified clock signal independent of a pulse width of the clock signal.
Claim 25
Dependent Claim
117 words
A circuit comprising: a latch which receives an input signal; and a pulse generation circuit which receives a clock signal and outputs a modified clock signal to the latch, and; wherein a timing of a rising (or falling) edge of said modified clock signal is determined by a timing of a rising (or falling) edge of said clock signal, a timing of a falling (or rising) edge of said modified clock signal is determined by a timing of a rising (or falling) edge of said clock signal, and wherein the latch holds the input signal for a predetermined period of time as determined by the modified clock signal independent of a pulse width of the clock signal.
Claim 26
Dependent Claim
70 words
A circuit for use in conjunction with a synchronous random access memory device comprising: a latch which receives an input signal; and a pulse generation circuit which receives a clock signal and outputs a modified clock signal to the latch, wherein the latch holds the input signal for a predetermined period of time as determined by the modified clock signal and responsive only to rising edges of the clock signal.
Claim 27
Dependent Claim
70 words
A circuit for use in conjunction with a synchronous random access memory device comprising: a latch which receives an input signal; and a pulse generation circuit which receives a clock signal and outputs a modified clock signal to the latch, wherein the latch holds the input signal for a predetermined period of time as determined by the modified clock signal and responsive only to rising edges of the clock signal.
Claim 28
Dependent Claim
15 words
The circuit according to claim 21, wherein the input signal is a delayed address signal.
Claim 29
Dependent Claim
29 words
The circuit according to claim 21, wherein the predetermined period of time corresponds to a time period necessary to accurately carry out a read/write operation using the input signal.
Claim 30
Dependent Claim
71 words
A circuit for use in conjunction with a synchronous random access memory device comprising: a latch which receives an input signal; and a phase locked loop circuit which receives a clock signal and outputs a modified clock signal to the latch, wherein the latch holds the input signal for a predetermined period of time as determined by the modified clock signal and responsive only to rising edges of the clock signal.
Claim 31
Dependent Claim
71 words
A circuit for use in conjunction with a synchronous random access memory device comprising: a latch which receives an input signal; and a phase locked loop circuit which receives a clock signal and outputs a modified clock signal to the latch, wherein the latch holds the input signal for a predetermined period of time as determined by the modified clock signal and responsive only to rising edges of the clock signal.
Claim 32
Dependent Claim
15 words
The circuit according to claim 24, wherein the input signal is a delayed address signal.
Claim 33
Dependent Claim
29 words
The circuit according to claim 24, wherein the predetermined period of time corresponds to a time period necessary to accurately carry out a read/write operation using the input signal.
Claim 34
Dependent Claim
71 words
A circuit for use in conjunction with a synchronous random access memory device comprising: a latch which receives an input signal; and a delay locked loop circuit which receives a clock signal and outputs a modified clock signal to the latch, wherein the latch holds the input signal for a predetermined period of time as determined by the modified clock signal and responsive only to rising edges of the clock signal.
Claim 35
Dependent Claim
71 words
A circuit for use in conjunction with a synchronous random access memory device comprising: a latch which receives an input signal; and a delay locked loop circuit which receives a clock signal and outputs a modified clock signal to the latch, wherein the latch holds the input signal for a predetermined period of time as determined by the modified clock signal and responsive only to rising edges of the clock signal.
Claim 36
Dependent Claim
15 words
The circuit according to claim 27, wherein the input signal is a delayed address signal.
Claim 37
Dependent Claim
29 words
The circuit according to claim 27, wherein the predetermined period of time corresponds to a time period necessary to accurately carry out a read/write operation using the input signal.
Claim 38
Dependent Claim
10 words
A computer system incorporating the semiconductor device of claim 1.
Claim 39
Dependent Claim
10 words
A computer system incorporating the semiconductor device of claim 12.
Claim 40
Dependent Claim
9 words
A computer system incorporating the SRAM of claim 14.
Claim 41
Dependent Claim
19 words
A computer system incorporating the circuit used in conjunction with a synchronous random access memory device of claim 20.
Claim 42
Dependent Claim
101 words
A semiconductor device operating synchronously with an external clock signal and having means for holding a signal input from an external unit, and comprising a holding-period control signal generation circuit for generating a holding-period control signal for controlling an input signal holding period independently of a pulse width of external clock signal, and wherein said input signal holding period starts at a first predetermined time after a predetermined rising or falling portion of said external clock signal, and said input signal holding period ends at a second predetermined time after said predetermined rising or falling portion of said external clock signal.
Claim 43
Dependent Claim
101 words
A semiconductor device operating synchronously with an external clock signal and having means for holding a signal input from an external unit, and comprising a holding-period control signal generation circuit for generating a holding-period control signal for controlling an input signal holding period independently of a pulse width of external clock signal, and wherein said input signal holding period starts at a first predetermined time after a predetermined rising or falling portion of said external clock signal, and said input signal holding period ends at a second predetermined time after said predetermined rising or falling portion of said external clock signal.
References Cited (Backward Citations)
US4996672A
Cited
US5124669A
Cited
US5446867A
Cited
JPH0620479A
Cited
JPH0667670A
Cited
US5708622A
Cited
US5619170A
Cited
US5740115A
Cited
US5566108A
Cited
US5754838A
Cited
US5621698A
Cited
US5717652A
Cited
US5729500A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-07-05 | 2003-01-04 | 2003-07-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-07-05 | 2007-01-04 | 2007-07-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-07-05 | 2011-01-04 | 2011-07-06 | $7700.00 | Window Closed / Lapsed |