PLL timing generator with voltage controlled oscillator

Claim 1

A phase lock loop timing generator, comprising: a phase comparator, a charging pump, a low-pass filter, and a voltage controlled oscillator (VCO), the phase comparator, the charging pump and the low-pass filter connected in a series arrangement and configured to detect a phase difference between an external clock signal and an internal clock signal and based on the detected phase difference, and to generate an input voltage Vin for the VCO, the VCO including a voltage-current converter and a current-limited ring oscillator, in the voltage-current converter, a variation of the input voltage Vin being converted into control currents Ip and In, the current-limited ring oscillator having a plurality of inverters connected in series in a ring arrangement, wherein phase-shifted signals output from nodes of the inverters are logically calculated to produce clock cycle proportional pulses (CCPP) proportional to a clock cycle of the external clock signal cycle, buffers, connected on a one-to-one basis to the nodes of the inverters, for making loads of the inverters uniform to equalize delay times, and a delay circuit connected to the buffers for providing a clock edge lookahead pulse (CELP) which is equal to a minimum pulse width of the internal clock signal, wherein by using the phase-shifted signals output from the nodes of first and second predetermined stages of the inverters from which the internal clock signal is output, a timing prior to a reference clock edge is generated.