Pulse generating circuit in a semiconductor integrated circuit and a delay circuit therefor

Claim 1

A pulse generating circuit in a semiconductor integrated circuit comprising: a first input terminal for receiving a first signal, a delay circuit receiving the first signal and producing a second signal delayed with respect to the first signal, the delay circuit having delay time which is variable by a control signal supplied from the outside, control means connected for supplying the control signal to the delay circuit to vary the delay time, and logic circuit means for receiving the first and the second signals and producing a pulse having a duration corresponding to the delay time of the second signal with respect to the first signal, wherein the delay circuit comprises an input terminal, an output terminal, a plurality of MOS transistor switching circuits connected in parallel with each other, the parallel connection of the MOS transistor switching circuits being connected between the input and the output terminal, a capacitance element connected between the output terminal and a power source terminal, and conduction control means for controlling the conduction of the MOS transistor switching circuits to vary the overall resistance of the parallel connection of the MOS transistor switching circuits.