Delay device and the use thereof in the decoding device of distance measuring equipment

Claim 3

A delay device as claimed in claim 1, wherein said means for acquiring the signal comprise: an M stage shift register, comprising M series connected storage circuits controlled by the same signal of given frequency f e , whose role is to sample the electric signal and to convert it into binary words each comprising M bits; a buffer memory with M stages comprising M parallel connected storage circuits, controlled by the same signal of frequency f m , such that: f.sub.m =(f.sub.e /M) this signal of frequency f m being moreover synchronous with the signal of frequency f e and the parallel inputs of the M storage circuits of the buffer memory being connected respectively to the M outputs of the storage circuits of the shift register, this buffer memory storing temporarily each binary word of M bits transiting between the shift register and the storage means of the delay device.

Claim 4

A delay device as claimed in claim 1 or 2, characterized in that the means for storing the signal in the form of M bit binary words comprise: M addressable random access memories, connected in parallel, controlled by the same signal of frequency f m , synchronous with the signals for controlling the acquisition means, the inputs of each of the memories being connected respectively to the M parallel outputs of the acquisition means; a circuit for addressing said random access memories, controlled by a signal of frequency f m synchronous with the preceding control signal and presenting to each, at each period of said control signal, a distinct reading address a and writing address a'; a control circuit for reading and writing the binary words appearing at the output of the acquisition means, controlled by a signal of frequency f m , synchronous with the preceding control signal, and connected to each of the memories.

Claim 5

A delay device according to claim 1 wherein said addressing circuit comprises: a reading counter, a writing counter, each initialized at a value such that the difference between the writing address for one binary word and that for reading same is equal to a given number of periods of the control signal, a routing circuit for the reading and writing addresses, receiving as input the addresses from the two counters and delivering at the output a single one of these two addresses to each of the memories.

Claim 6

A delay device as in claim 1 wherein said routing circuit comprises a first AND gate receiving as input the address of the reading counter and the control signal of frequency f m ; a second AND gate receiving as input the address from the writing counter and the signal of frequency f m after it has passed through an inverter circuit; an OR gate receiving as input the output signals from the two AND gates and outputting one of the reading or writing addresses.

Claim 7

A delay device as in claim 1 wherein the means for restoring the signal comprise a shift register with M stages, comprising M parallel connected storage circuits, controlled by the same signal of frequency f m synchronous with the preceding control signals the inputs of the M storage circuits being connected respectively to the M parallel outputs of the storage means, whose role is that of a buffer memory; a multiplexer controlled by a delivered signal of frequency f e synchronous with the preceding control signal, whose n inputs are connected respectively to the outputs of the M storage circuits of said shift register and whose output delivers the electric signal.

Claim 8

Application of the delay device as in claim 1 to a decoding device for a transponder forming part of distance measuring equipment, wherein: the frequency f e is equal to 32 MHz, frequency f m is equal to 8 MHz, the number n is equal to 4.