US4633308A
Expired / Lapsed
US
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Amplitude insensitive delay lines in an accoustic imaging system
Assignee: HP Inc
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Filing: 1984-07-05
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Granted: 1986-12-30
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Expires: 2004-07-05
Abstract
Abstract A delay circuit for providing signal delay within an acoustic imaging system is provided. Reflected acoustic signals are transformed into electrical signals and are used to reproduce images of objects. Delay lines along the electrical signal path are used to focus the images compensating for asynchronism of electrical signals caused by variations in the length of acoustic signal paths.
Inventors
- 👤 John N. Dukes
- 👤 Richard A. Baumgartner
- 👤 Ian Bennett
- 👤 Richard D. Pering
- 👤 George A. Fisher
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 15:50
CPC Classifications
G; G01; G01S; G01S7/00; G01S7/52; G01S7/52003; H; H03; H03H; H03H11/00; H03H11/02; H03H11/26; H03K; H03K5/00; H03K5/13; H03K5/131; H03K7/00; H03K7/06; H03K7/08; H03K2005/00013; H03K2005/0015; H03K2005/00195
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
93 words
In an acoustic imaging system, a combination comprising: a plurality of delay circuits, each delay circuit comprising a plurality of unclocked cascaded saturating circuit elements; a plurality of transducing means for receiving acoustic pulses and transforming them into pulse width modulated signals each transducing means being coupled to an associated delay circuit from the plurality of delay circuits and each transducing means coupling the electrical pulses onto its associated delay circuit; and, a summing means coupled to the plurality of delay circuits for resistive summing electrical signals from the plurality of delay circuits.
Claim 2
Dependent Claim
93 words
In an acoustic imaging system, a combination comprising: a plurality of delay circuits, each delay circuit comprising a plurality of unclocked cascaded saturating circuit elements; a plurality of transducing means for receiving acoustic pulses and transforming them into pulse width modulated signals each transducing means being coupled to an associated delay circuit from the plurality of delay circuits and each transducing means coupling the electrical pulses onto its associated delay circuit; and, a summing means coupled to the plurality of delay circuits for resistive summing electrical signals from the plurality of delay circuits.
Claim 3
Dependent Claim
29 words
A combination as in claim 1 wherein each delay circuit has a control means for varying the length of propagation delay for a signal traveling through that delay circuit.
Claim 4
Dependent Claim
42 words
A combination as in claim 2 additionally comprising a plurality of transforming means for transforming analog signals into binary signals, wherein every transforming means from the plurality of transforming means is coupled to a transducing means from the plurality of transducing means.
Claim 5
Dependent Claim
71 words
A combination as in claim 3 wherein each element of the plurality of saturating circuit elements in each delay circuit in the plurality of delay circuits delays the signal passing through that delay circuit for a length of time substantially the same as the length of time the signal passing through that delay circuit is delayed by every other element of the plurality of saturating circuit elements in that delay circuit.
Claim 6
Dependent Claim
98 words
A combination as in claim 4 wherein: each delay circuit in the plurality of delay circuits additionally comprises: an input means for coupling the signal to the plurality of cascaded saturating circuit elements, and an output means for coupling the signal to a subsequent circuit; and wherein the control means comprises: a plurality of taps at intervals of delay along the plurality of cascaded saturating circuit elements, and a switching means coupled to the plurality of taps and to the output means for selecting a tap from the plurality of taps to be coupled to the output means.
Claim 7
Dependent Claim
17 words
A combination as in claim 5 wherein the plurality of taps are at equal intervals of delay.
Claim 8
Dependent Claim
20 words
A combination as in claim 1 wherein each saturating circuit element in the plurality of delay circuits comprises an inverter.
Claim 9
Dependent Claim
51 words
A circuit as in claim 7 wherein each element additionally comprises: control means for varying delay having a first node coupled to a voltage source, a second node coupled to the inverter and a third node on which may be placed a signal in order to vary delay through the inverter.
Claim 10
Dependent Claim
118 words
In an acoustic imaging system, a combination comprising: a plurality of delay circuits, each delay circuit comprising a plurality of cascaded saturating circuit elements, wherein each cascaded saturating circuit element includes control means for varying delay through the saturating circuit element in response to a signal coupled to the control means; a plurality of transducing means for receiving acoustic pulses and transforming them into modulated electrical signals each transducing means being coupled to an associated delay circuit from the plurality of delay circuits and each transducing means coupling the modulated electrical signal onto its associated delay circuit; and, a summing means coupled to the plurality of delay circuits for summing electrical signals from the plurality of delay circuits.
Claim 11
Dependent Claim
118 words
In an acoustic imaging system, a combination comprising: a plurality of delay circuits, each delay circuit comprising a plurality of cascaded saturating circuit elements, wherein each cascaded saturating circuit element includes control means for varying delay through the saturating circuit element in response to a signal coupled to the control means; a plurality of transducing means for receiving acoustic pulses and transforming them into modulated electrical signals each transducing means being coupled to an associated delay circuit from the plurality of delay circuits and each transducing means coupling the modulated electrical signal onto its associated delay circuit; and, a summing means coupled to the plurality of delay circuits for summing electrical signals from the plurality of delay circuits.
Claim 12
Dependent Claim
64 words
A combination as in claim 9 wherein each delay circuit in the plurality of delay circuits includes: a plurality of taps at intervals of delay along the plurality of cascaded saturating circuit elements, and a switching means coupled to the plurality of taps and to the output means for selecting a tap from the plurality of taps to be coupled to the output means.
Claim 13
Dependent Claim
17 words
A combination as in claim 10 wherein the plurality of taps are at equal intervals of delay.
Claim 14
Dependent Claim
20 words
A combination as in claim 9 wherein each saturating circuit element in the plurality of delay circuits comprises an inverter.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-12-29 | 1990-06-30 | 1990-12-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-12-29 | 1994-06-30 | 1994-12-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-12-29 | 1998-06-30 | 1998-12-30 | $7700.00 | Window Closed / Lapsed |