US5621698A
Expired / Lapsed
US
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Data signal distribution circuit for synchronous memory device
Assignee: SK Hynix Inc
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Filing: 1995-12-28
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Granted: 1997-04-15
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Expires: 2015-12-28
Abstract
Abstract A data signal distribution circuit for a synchronous memory device comprising a data generation source for generating successive data signals in response to an external clock signal. The data signal distribution circuit comprises at least two control switches for switching the data signals from the data generation source to at least two peripheral circuits, a strobe signal generator for delaying the external clock signal by a propagation delay time of the data generation source and generating a strobe signal in response to the delayed external clock signal, and an internal address generator for generating an internal address signal in response to the strobe signal from the strobe signal generator and supplying the generated internal address signal to the control switches. The strobe signal has a predetermined logic level for a predetermined duration beginning with a pulse edge of the delayed external clock signal. The internal address signal has at least two bits, only one of which has the predetermined logic level.
Inventors
- 👤 Jae J. Lee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 03:04
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G11; G11C; G11C7/00; G11C7/10; G11C7/1006
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
211 words
In a synchronous memory device comprising a data generation source for generating successive data signals in response to an external clock signal, a data signal distribution circuit comprising: delay means for delaying the external clock signal by a propagation delay time of said data generation source; data conversion means for converting the data signals from said data generation source into true and complementary data signals in response to the delayed external clock signal from said delay means; at least two true switching means for transferring the true data signal from said data conversion means to peripheral circuits connected to at least two true output lines; at least two complementary switching means for transferring the complementary data signal from said data conversion means to peripheral circuits connected to at least two complementary output lines; logic combination means for logically combining the true and complementary data signals from said data conversion means to generate a data clock signal; and internal address generation means for generating an internal address signal in response to the data clock signal from said logic combination means and supplying the generated internal address signal to said true and complementary switching means, said internal address signal having at least two bits, only one of which has a predetermined logic level.
Claim 2
Dependent Claim
211 words
In a synchronous memory device comprising a data generation source for generating successive data signals in response to an external clock signal, a data signal distribution circuit comprising: delay means for delaying the external clock signal by a propagation delay time of said data generation source; data conversion means for converting the data signals from said data generation source into true and complementary data signals in response to the delayed external clock signal from said delay means; at least two true switching means for transferring the true data signal from said data conversion means to peripheral circuits connected to at least two true output lines; at least two complementary switching means for transferring the complementary data signal from said data conversion means to peripheral circuits connected to at least two complementary output lines; logic combination means for logically combining the true and complementary data signals from said data conversion means to generate a data clock signal; and internal address generation means for generating an internal address signal in response to the data clock signal from said logic combination means and supplying the generated internal address signal to said true and complementary switching means, said internal address signal having at least two bits, only one of which has a predetermined logic level.
Claim 3
Dependent Claim
38 words
A data signal distribution circuit as set forth in claim 1, further comprising address synchronization means for synchronizing the internal address signal from said internal address generation means with the delayed external clock signal from said delay means.
Claim 4
Dependent Claim
86 words
A data signal distribution circuit as set forth in claim 1, wherein each of said true and complementary switching means includes first and second MOS transistors connected between a supply voltage source and a corresponding one of said true and complementary output lines, said first MOS transistor being driven in response to the internal address signal from said internal address generation means, said second MOS transistor being driven in response to a corresponding one of the true and complementary data signals from said data conversion means.
Claim 5
Dependent Claim
56 words
A data signal distribution circuit as set forth in claim 3, further comprising at least four storage means, each of said storage means holding a corresponding one of the true and complementary data signals on said true and complementary output lines, transferred by said first and second MOS transistors in said true and complementary switching means.
Claim 6
Dependent Claim
87 words
A data signal distribution circuit as set forth in claim 4, wherein each of said true and complementary switching means further includes a third MOS transistor connected between a ground voltage source and a corresponding one of said true and complementary output lines, for initializing the true or complementary data signal on said corresponding true or complementary output line, held by a corresponding one of said storage means, in response to a reset signal from the peripheral circuit connected to said corresponding true or complementary output line.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-04-14 | 2000-10-14 | 2001-04-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-04-14 | 2004-10-14 | 2005-04-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-04-14 | 2008-10-14 | 2009-04-15 | $7700.00 | Window Closed / Lapsed |