Memory interface unit, shared memory switch system and associated method

Claim 2

An interface unit comprising: terminals T1; terminals T2; one or more terminals T3; and a configurable switch such that: in a first configuration, a data word received by the switch on the terminals T1 is transferred to the terminals T2; and in a second configuration, a portion of a data word received by the switch on the terminals T1 is transferred to one or more terminals T2, and another portion of the same data word is transferred to one or more terminals T3.

Claim 3

The interface unit of claim 1 wherein one or more terminals T1 are to receive data from a memory, or one or more terminals T2 are to provide data to a memory.

Claim 4

The interface unit of claim 2 wherein one or more terminals T1 are to receive data from one or more network interface units, or one or more terminals T2 are to provide data to one or more network interface units, thus allowing the switch to transfer data between the memory and the one or more network interface units.

Claim 5

The interface unit of claim 3 in combination with the memory and the one or more network interface units.

Claim 6

The unit of claim 1 wherein: data transferred by the switch to one or more terminals T2 are written to a first memory; and in the second configuration, data transferred by the switch to one or more terminals T3 are written to a second memory.

Claim 7

The unit of claim 1 wherein: in the first configuration, a data word received by the switch on the terminals T2 is transferred by the switch to the terminals T1; and in the second configuration, the switch receives a portion of a data word on one or more terminals T2 and another portion of the same data word on one or more terminals T3, and the switch transfers both portions to the terminals T1.

Claim 8

The unit of claim 6 in combination with one or more other units each of which has (a) terminals T1, (b) terminals T2, (c) one or more terminals T3, and (d) a switch which is to receive a data word on the terminals T1 of the unit and to transfer a portion of the data word to one or more terminals T2 of the unit and to transfer another portion of the same data word to one or more terminals T3 of the unit, wherein each of said units has one or more terminals T4 coupled to one or more terminals T3 of one or more other units, and the switch of each unit transfers data from one or more terminals T4 of the unit to one or more terminals T2 of the unit, so that a data word received on the terminals T1 of any one of the units has a portion transferred to one or more terminals T2 of every unit, and the units are capable to receive portions of a data word on one or more terminals T2 of each unit and to transfer the portions to the terminals T1 of any one of the units.

Claim 9

The unit of claim 1 in combination with one or more other units each of which has (a) terminals T1, (b) terminals T2, (c) one or more terminals T3, and (d) a switch which is to receive a data word on the terminals T1 of the unit and to transfer a portion of the data word to one or more terminals T2 of the unit and to transfer another portion of the same data word to one or more terminals T3 of the unit, wherein each of said units has one or more terminals T4 coupled to one or more terminals T3 of one or more other units, and the switch of each unit transfers data from one or more terminals T4 of the unit to one or more terminals T2 of the unit, so that a data word received on the terminals T1 of any one of the units has a portion transferred to one or more terminals T2 of every unit.

Claim 10

An interface unit comprising: terminals T1; terminals T2; one or more terminals T3; and a configurable switch such that: in a first configuration, a data word received by the switch on the terminals T2 is transferred by the switch to the terminals T1; and in a second configuration, the switch receives a portion of a data word on one or more terminals T2 and another portion of the same data word on one or more terminals T3, and the switch transfers both portions to the terminals T1.

Claim 11

An interface unit comprising: terminals T1; terminals T2; one or more terminals T3; and a configurable switch such that: in a first configuration, a data word received by the switch on the terminals T2 is transferred by the switch to the terminals T1; and in a second configuration, the switch receives a portion of a data word on one or more terminals T2 and another portion of the same data word on one or more terminals T3, and the switch transfers both portions to the terminals T1.

Claim 12

The interface unit of claim 9 wherein one or more terminals T1 are to receive data from a memory, or one or more terminals T2 are to provide data to a memory.

Claim 13

The interface unit of claim 10 wherein one or more terminals T1 are to receive data from one or more network interface units, or one or more terminals T2 are to provide data to one or more network interface units, thus allowing the switch to transfer data between the memory and the one or more network interface units.

Claim 14

The unit of claim 11 in combination with the memory and the one or more network interface units.

Claim 15

The unit of claim 9 wherein: data received by the switch on one or more terminals T2 are from a first memory; and in the second configuration, data received by the switch on one or more terminals T3 are from a second memory.

Claim 16

The interface unit of claim 9 in combination with one or more other interface units each of which has (a) terminals T1, (b) terminals T2, (c) one or more terminals T3, and (d) a switch which is to receive a portion of a data word on one more terminals T2 of the unit and another portion of the same data word on one or more terminals T3 of the unit and to transfer both portions to the terminals T1 of the unit; wherein each of said units has one or more terminals T4 coupled to one or more terminals T3 of one or more other units, and the switch of each unit transfers data from one or more terminals T2 of the unit to one or more terminals T4 of the unit, so that the units are capable of receiving portions of a data word on one or more terminals T2 of each unit and to transfer the portions to the terminals T1 of the unit U1.

Claim 17

An interface unit U1 to be used by itself or in combination with one or more other such interface units, the unit U1 comprising: terminals T1; terminals T2; one or more ports P, wherein each port P is capable of being coupled to a port P of another interface unit; and a configurable switch such that: in a first configuration, the switch provides a data path between each terminal T1 and a respective terminal T2 to enable data to be transferred between all of the terminals T1 and all of the terminals T2; and in a second configuration, the switch provides: (1) one or more first data paths between a set T1-1 of one or more terminals T1 and a set T2-1 of one or more terminals T2, (2) one or more second data paths between: (i) a set T1-2 of one or more terminals T1 and (ii) one or more ports P, and (3) one or more third data paths between: (i) a set T2-2 of one or more terminals T2 and (ii) one or more ports P, such that when one or more ports P of the unit U1 are coupled to one or more ports P of one or more other such interface units: (a) data appearing on the set T1-1 of the unit U1 are data transferred between the set T1-1 and of the unit U1 and the set T2-1 of the unit U1; (b) data appearing on the set T1-2 of the unit U1 are data transferred between the set T1-2 of the unit U1 and one or more terminals T2 of one or more other units; and (c) data appearing on the set T2-2 of the unit U1 are data transferred between the set T2-2 of the unit U1 and one or more terminals T1 of one or more other units.

Claim 18

An interface unit U1 to be used by itself or in combination with one or more other such interface units, the unit U1 comprising: terminals T1; terminals T2; one or more ports P, wherein each port P is capable of being coupled to a port P of another interface unit; and a configurable switch such that: in a first configuration, the switch provides a data path between each terminal T1 and a respective terminal T2 to enable data to be transferred between all of the terminals T1 and all of the terminals T2; and in a second configuration, the switch provides: (1) one or more first data paths between a set T1-1 of one or more terminals T1 and a set T2-1 of one or more terminals T2, (2) one or more second data paths between: (i) a set T1-2 of one or more terminals T1 and (ii) one or more ports P, and (3) one or more third data paths between: (i) a set T2-2 of one or more terminals T2 and (ii) one or more ports P, such that when one or more ports P of the unit U1 are coupled to one or more ports P of one or more other such interface units: (a) data appearing on the set T1-1 of the unit U1 are data transferred between the set T1-1 and of the unit U1 and the set T2-1 of the unit U1; (b) data appearing on the set T1-2 of the unit U1 are data transferred between the set T1-2 of the unit U1 and one or more terminals T2 of one or more other units; and (c) data appearing on the set T2-2 of the unit U1 are data transferred between the set T2-2 of the unit U1 and one or more terminals T1 of one or more other units.

Claim 19

The interface unit U1 of claim 15 in combination with the one or more other units, wherein every unit is coupled through its one or more ports P to every other unit.

Claim 20

The interface unit U1 of claim 15 wherein each of said data paths is bidirectional.

Claim 21

The interface unit U1 of claim 15 wherein the terminals T2 of each interface unit are to provide data to, and/or receive data from, a memory connected to the unit, so that: in the first configuration, an entire data word on the terminals T1 of the unit U1 is transferred through the terminals T2 between the terminals T1 and the memory coupled to the unit U1; and in the second configuration, a first portion of a word appearing on the terminals T1 of the unit U1 is transferred between the terminals T1 and the memory coupled to the unit U1, and a second portion of the word is transiterred between the terminals T1 of the unit U1 and one or more memories coupled to one or more other units.

Claim 22

The interface unit U1 of claim 15 further comprising a circuit for coupling the terminals T1 to one or more network interface units.

Claim 23

The unit U1 of claim 15 in combination with the one or more other units, wherein: each of the units is coupled through its one or more ports P to one or more other units; and each unit has an address bus for receiving an address for a memory to be coupled to the unit, and the address buses of all the units are interconnected to provide the same address to all the units.

Claim 24

The interface unit of claim 6, wherein the unit is a memory interface unit further comprising: a bus interface unit; a buffer which can store multiple data burst subsets in transit to or from a digital memory; and one or more slave terminals T4; wherein the switch includes a master data path which transfers data between the bus interface unit and one or more terminals T3, a slave data path which transfers data between the buffer and one or more slave terminals T4, and a direct data path which transfers data between the bus interface unit and the buffer.

Claim 25

The memory interface unit of claim 21, wherein the buffer includes an input storage element which can store multiple data burst subsets in transit to a digital memory and an output storage element which can store multiple data burst subsets in transit from the digital memory.

Claim 26

The interface unit of claim 6, wherein the unit is a memory interface unit further comprising: a bus interface unit; a buffer which includes multiple input storage elements each of which can store a data burst subset in transit to a digital memory and multiple output storage elements each of which can store a data burst subset in transit from the digital memory; and slave terminals T4; wherein the switch includes: (1) multiple master data paths which transfer data between the bus interface unit and multiple terminals T3, (2) multiple slave data paths which transfer data between multiple terminals T4 and the buffer, and (3) multiple direct data paths which transfer data between the bus interface unit and the buffer.

Claim 27

The memory interface unit of claim 21, wherein the master data path is optionally connectable to the bus interface unit.

Claim 28

The memory interface unit of claim 21, wherein the slave data path is optionally connectable to the buffer.

Claim 29

The memory interface unit of claim 21, wherein the direct data path is optionally connectable between the bus interface unit and the buffer.

Claim 30

The memory interface unit of claim 21, wherein the master data path is optionally connectable to the bus interface unit; wherein the slave data path is optionally connectable to the buffer; and wherein the direct data path is optionally connectable between the bus interface unit and the buffer.

Claim 31

The memory interface unit of claim 21, wherein the master data path both transfers data to the bus interface unit and transfers data from the bus interface unit.

Claim 32

The memory interface unit of claim 21, wherein the slave data path both transfers data to the buffer and transfers data from the buffer.

Claim 33

The memory interface unit of claim 21, wherein the master data path both transfers data to the bus interface unit and transfers data from the bus interface unit; and wherein the slave data path both transfers data to the buffer and transfers data from the buffer.

Claim 34

The memory interface unit of claim 22, wherein the slave data path transfers data both to the buffer input storage element and transfers data from the buffer output storage element.

Claim 35

The memory interface unit of claim 23, wherein each master data path is optionally connectable between the bus interface unit and one or more terminals T3; wherein each slave data path is optionally connectable between either a buffer input storage element or a buffer output storage element and one or more terminals T4; and wherein each direct data path is optionally connectable between the bus interface unit and the buffer.

Claim 36

The memory interface unit of claim 23, wherein each master data path both transfers data to the bus interface unit and transfers data from the bus interface unit; wherein each slave data path transfers data both to a buffer input storage element and transfers data from a buffer output storage element; and wherein each direct data path both transfers data to a buffer input storage element and transfers data from a buffer output storage element.

Claim 37

The interface unit of claim 6, wherein the unit is an electronic interface unit for use between digital memory and a bus, the electronic interface unit further comprising a buffer which includes multiple storage elements each of which can store a data burst subset in transit between the digital memory and the bus; and wherein the switch is configurable to provide a direct data path between a respective storage element and the bus or to provide both an externally accessible slave data path to and from the respective storage element and an externally accessible master data path to and from the bus.

Claim 38

The electronic interface unit of claim 34 further including a bus interface register connected between the bus and the terminals T1.

Claim 39

The electronic interface unit of claim 34, wherein each buffer storage element includes an input storage element and an output storage element.

Claim 40

The interface unit of claim 34, further comprising parallel data path circuitry connectable between a respective storage element and the digital memory, said parallel data path being wide enough to conduct an entire data burst subset.

Claim 41

The electronic interface unit of claim 37, wherein the direct, master and slave paths each is multiple bits wide.

Claim 42

The electronic interface unit of claim 37, wherein the direct, master and slave paths each is wide enough to conduct only a data burst subset fragment.

Claim 43

The electronic interface unit of claim 37 further including a bus interface register connected between the bus and the terminals T1.

Claim 44

The electronic interface unit of claim 37 further including: controller circuitry which controls the transfer of data between the buffer and the switch and which controls the transfer of data between the buffer and the digital memory.

Claim 45

The electronic interface unit of claim 37, wherein respective storage elements include respective serial transfer circuitry which serially transfers data burst subset fragments to and from said switch.

Claim 46

The electronic interface unit of claim 37, wherein respective storage elements include respective shift-in register circuitry connected to serially shift in data burst subset fragments from either a respective direct data path or from a respective slave data path and include respective shift-out circuitry connected to serially shift out data burst subset fragments to either a direct data path or to a slave data path.

Claim 47

The electronic interface unit of claim 37, wherein respective storage elements include respective serial shift-in/parallel shift-out circuitry connected to serially shift in data burst subset fragments from either a respective direct data path or from a respective slave data path and to parallel shift-out entire data burst subsets to the digital memory; and wherein respective storage elements include respective parallel shift-in/serial shift-out circuitry connected to parallel shift-in entire data burst subsets and to serially shift out data burst subset fragments to either a direct data path or to a slave data path.

Claim 48

The electronic interface unit of claim 37, wherein respective storage elements include respective serial shift-in/parallel shift-out circuitry connected to serially shift in data burst subset fragments from either a respective direct data path or from a respective slave data path and to parallel shift-out entire data burst subsets to the digital memory; and wherein respective storage elements include respective parallel shift-in/serial shift-out circuitry connected to parallel shift-in entire data burst subsets and to serially shift out data burst subset fragments to either a direct data path or to a slave data path; wherein the parallel data path circuitry intermittently connects respective serial shift-in/parallel shift-out circuitry with the digital memory; and wherein the parallel data path circuitry intermittently connects respective serial shift-in/parallel shift-out circuitry with the digital memory.

Claim 49

The interface unit of claim 21 further comprising a multiplexer to multiplex between data paths.

Claim 50

A digital signal queue management unit comprising the interface unit of claim 6 and also comprising: digital memory; a bus interface; a buffer which includes multiple storage elements each of which can store a data burst subset in transit between the digital memory and the bus interface; wherein the switch provides one or more respective direct data paths between respective storage elements and the bus interface and provides both one or more respective corresponding externally accessible slave data paths to and from such respective storage elements and one or more respective corresponding externally accessible master data paths to and from the bus interface.

Claim 51

The digital signal queue management unit of claim 47 further including: controller means for controlling the transfer of data between the buffer and the terminals T2 and for controlling the transfer of data between the buffer and the digital memory.

Claim 52

The digital signal queue management unit of claim 47 further including: address means for providing a digital address received at the bus interface to the digital memory.