Multiple-port shared memory interface and associated method

Claim 2

For use in a multi-port memory system which includes random access memory (RAM) and multiple data ports, a memory interface comprising: multiple buffers, each including multiple storage elements for simultaneous storage of multiple respective data burst subsets transmitted between different respective data ports and said RAM, and further including parallel data path circuitry connectable between individual storage elements and said RAM; and an interconnect circuit which includes a multiplicity of data lines which interconnect each respective data port with multiple respective buffers such that different respective subsets of any given data burst transmitted between a respective data port and said RAM are conducted to or from different respective buffers via different respective data lines.

Claim 3

The system of claim 1 wherein respective storage elements include serial transfer circuitry which serially transfers data burst subsets to and from said interconnect circuit.

Claim 4

The system of claim 1 wherein respective storage elements include respective shift-in register circuitry for serially shifting in respective data burst subsets from said interconnect circuit and include respective shift-out register circuitry for serially shifting out respective data burst subsets to said interconnect circuit.

Claim 5

The system of claim 1 wherein respective storage elements include respective serial shift-in/parallel shift-out register circuitry for serially shifting in respective data burst subsets from said interconnect circuit and for parallel shift out of such data burst subsets to said RAM; and wherein respective storage elements further include respective parallel shift-in/serial shift-out register circuitry for parallel shift in of respective data burst subsets from said RAM and for serially shifting out such data burst subsets to said interconnect circuit.

Claim 6

The system of claim 1, wherein respective storage elements include respective serial shift-in/parallel shift-out register circuitry for serially shifting in respective data burst subsets from said interconnect circuit and for parallel shift out of such data burst subsets to said RAM; wherein respective storage elements further include respective parallel shift-in/serial shift-out register circuitry for parallel shift in of respective data burst subsets from said RAM and for serially shifting out such data burst subsets to said interconnect circuit; wherein respective parallel data path circuitry intermittently connects respective serial shift-in/parallel shift-out register circuitry with said RAM; and wherein respective parallel data path circuitry intermittently connects respective parallel shift-in/serial shift-out register circuitry with said RAM.

Claim 7

The system of claim 1 wherein respective storage elements include serial transfer circuitry which serially transfers data burst subsets one bit at a time to and from said interconnect circuit.

Claim 8

The system of claim 1 wherein said interconnect circuit includes a printed circuit board.

Claim 9

For use in a multi-port memory system which includes random access memory (RAM) and multiple data ports, a memory interface comprising: multiple buffers, each including multiple storage elements for simultaneous storage of multiple respective data burst subsets in transit between different respective data ports and said RAM, respective storage elements including respective serial shift-in/parallel shift-out register circuitry for serially shifting in respective data burst subsets from said interconnect circuit and for parallel shift out of such data burst subsets to said RAM, respective storage elements further including respective parallel shift-in/serial shift-out register circuitry for parallel shift in of respective data burst subsets from said RAM and for serially shifting out such data burst subsets to said interconnect circuit, said respective buffers further including respective parallel data path circuitry which intermittently connects respective serial shift-in/parallel shift-out register circuitry with said RAM and which intermittently connects respective parallel shift-in/serial shift-out register circuitry with said RAM; and a printed circuit board interconnect circuit which includes a multiplicity of data lines which interconnect each respective data port with multiple respective buffers such that different respective subsets of any given data burst in transit between a respective data port and said RAM are conducted to or from different respective buffers via different respective data lines.

Claim 10

For use in a multi-port memory system which includes random access memory (RAM) and multiple data ports, a memory interface comprising: multiple buffers, each including multiple storage elements for simultaneous storage of multiple respective data burst subsets in transit between different respective data ports and said RAM, respective storage elements including respective serial shift-in/parallel shift-out register circuitry for serially shifting in respective data burst subsets from said interconnect circuit and for parallel shift out of such data burst subsets to said RAM, respective storage elements further including respective parallel shift-in/serial shift-out register circuitry for parallel shift in of respective data burst subsets from said RAM and for serially shifting out such data burst subsets to said interconnect circuit, said respective buffers further including respective parallel data path circuitry which intermittently connects respective serial shift-in/parallel shift-out register circuitry with said RAM and which intermittently connects respective parallel shift-in/serial shift-out register circuitry with said RAM; and a printed circuit board interconnect circuit which includes a multiplicity of data lines which interconnect each respective data port with multiple respective buffers such that different respective subsets of any given data burst in transit between a respective data port and said RAM are conducted to or from different respective buffers via different respective data lines.

Claim 11

A multi-port memory system comprising: random access memory (RAM); multiple data ports; multiple buffers, each including multiple storage elements for simultaneous storage of multiple respective data burst subsets transmitted between different respective different respective data ports and said RAM, and further including parallel data path circuitry connectable between individual storage elements and said RAM; and an interconnect circuit which includes a multiplicity of data lines which interconnect each respective data port with multiple respective buffers such that different respective subsets of any given data burst transmitted between a respective data port and said RAM are conducted to or from different respective buffers via different respective data lines.

Claim 12

A multi-port memory system comprising: random access memory (RAM); multiple data ports; multiple buffers, each including multiple storage elements for simultaneous storage of multiple respective data burst subsets transmitted between different respective different respective data ports and said RAM, and further including parallel data path circuitry connectable between individual storage elements and said RAM; and an interconnect circuit which includes a multiplicity of data lines which interconnect each respective data port with multiple respective buffers such that different respective subsets of any given data burst transmitted between a respective data port and said RAM are conducted to or from different respective buffers via different respective data lines.

Claim 13

The system of claim 9, including a single RAM integrated circuit.

Claim 14

The system of claim 9 and further including: control circuitry which provides control signals that control simultaneous parallel transfer of all subsets of any given data burst between said RAM and multiple different buffers storing different subsets of such given data burst.

Claim 15

The system of claim 9 wherein respective storage elements include serial transfer circuitry which serially transfers data burst subsets to and from said interconnect circuit.

Claim 16

The system of claim 9 wherein said respective storage elements include serial transfer circuitry which serially transfers data burst subsets to and from said interconnect circuit; and further including: control circuitry which provides control signals that control simultaneous parallel transfer of all subsets of any given data burst between said RAM and multiple different buffers storing different subsets of such given data burst and which provides control signals that control transfer of data burst subsets between said interconnect circuitry and different respective buffers.

Claim 17

The system of claim 9 wherein respective storage elements include respective shift-in register circuitry for serially shifting in respective data burst subsets from said interconnect circuit and include respective shift-out register circuitry for serially shifting out respective data burst subsets to said interconnect circuit.

Claim 18

The system of claim 9 wherein respective storage elements include respective serial shift-in/parallel shift-out register circuitry for serially shifting in respective data burst subsets from said interconnect circuit and for parallel shift out of such data burst subsets to said RAM; and wherein respective storage elements further include respective parallel shift-in/serial shift-out register circuitry for parallel shift in of respective data burst subsets from said RAM and for serially shifting out such data burst subsets to said interconnect circuit.

Claim 19

The system of claim 9, wherein respective storage elements include respective serial shift-in/parallel shift-out register circuitry for serially shifting in respective data burst subsets from said interconnect circuitry and for parallel shift out of such data burst subsets to said RAM; wherein respective storage elements further include respective parallel shift-in/serial shift-out register circuitry for parallel shift in of respective data burst subsets from said RAM and for serially shifting out such data burst subsets to said interconnect circuit; wherein respective parallel data path circuitry intermittently connects respective serial shift-in/parallel shift-out register circuitry with said RAM; and wherein respective parallel data path circuitry intermittently connects respective parallel shift-in/serial shift-out register circuitry with said RAM.

Claim 20

The system of claim 9 wherein respective storage elements include serial transfer circuitry which serially transfers data burst subsets one bit at a time to and from said interconnect circuit.

Claim 21

The system of claim 9, wherein said interconnect circuit includes a printed circuit board.

Claim 22

A multi-port memory system comprising: random access memory (RAM); multiple data ports; multiple buffers, each including multiple storage elements for simultaneous storage of multiple respective data burst subsets transmitted between different respective data ports and said RAM, respective storage elements including respective serial shift-in/parallel shift-out register circuitry for serially shifting in respective data burst subsets from said interconnect circuit and for parallel shift out of such data burst subsets to said RAM, respective storage elements further including respective parallel shift-in/serial shift-out register circuitry for parallel shift in of respective data burst subsets from said RAM and for serially shifting out such data burst subsets to said interconnect circuit, each of said buffers further including respective parallel data path circuitry which intermittently connects respective serial shift-in/parallel shift-out register circuitry with said RAM and which intermittently connects respective parallel shift-in/serial shift-out register circuitry with said RAM; an interconnect circuit which includes a multiplicity of data lines which interconnect each respective data port with multiple respective buffers such that different respective subsets of any given data burst transmitted between a respective data port and said RAM are conducted to or from different respective buffers via different respective data lines; and control circuitry which provides control signals that control simultaneous parallel transfer of all subsets of any given data burst between said RAM and multiple different buffers storing different subsets of such given data burst and which provides control signals that control transfer of data burst subsets between said interconnect circuitry and different respective buffers.

Claim 23

A multi-port memory system comprising: random access memory (RAM); multiple data ports; multiple buffers, each including multiple storage elements for simultaneous storage of multiple respective data burst subsets transmitted between different respective data ports and said RAM, respective storage elements including respective serial shift-in/parallel shift-out register circuitry for serially shifting in respective data burst subsets from said interconnect circuit and for parallel shift out of such data burst subsets to said RAM, respective storage elements further including respective parallel shift-in/serial shift-out register circuitry for parallel shift in of respective data burst subsets from said RAM and for serially shifting out such data burst subsets to said interconnect circuit, each of said buffers further including respective parallel data path circuitry which intermittently connects respective serial shift-in/parallel shift-out register circuitry with said RAM and which intermittently connects respective parallel shift-in/serial shift-out register circuitry with said RAM; an interconnect circuit which includes a multiplicity of data lines which interconnect each respective data port with multiple respective buffers such that different respective subsets of any given data burst transmitted between a respective data port and said RAM are conducted to or from different respective buffers via different respective data lines; and control circuitry which provides control signals that control simultaneous parallel transfer of all subsets of any given data burst between said RAM and multiple different buffers storing different subsets of such given data burst and which provides control signals that control transfer of data burst subsets between said interconnect circuitry and different respective buffers.

Claim 24

A multi-port memory system comprising: random access memory (RAM); k data ports; m buffers, each including k storage elements for simultaneous storage of multiple respective n-bit subsets of n-word data bursts transmitted between different respective data ports and said RAM, and further including parallel data path circuitry connectable between individual storage elements and said RAM; wherein each respective n-bit subset consists of all n respective bits that occupy the same respective bit position in different respective data words of a respective n-word data burst; and an interconnect circuit which includes a multiplicity of data lines which interconnect each respective data port with m different buffers such that the m different respective n-bit subsets of any given m-word data burst transmitted between a respective data port and said RAM are conducted to or from m different respective buffers.

Claim 25

A multi-port memory system comprising: random access memory (RAM); k data ports; m buffers, each including k storage elements for simultaneous storage of multiple respective n-bit subsets of n-word data bursts transmitted between different respective data ports and said RAM, and further including parallel data path circuitry connectable between individual storage elements and said RAM; wherein each respective n-bit subset consists of all n respective bits that occupy the same respective bit position in different respective data words of a respective n-word data burst; and an interconnect circuit which includes a multiplicity of data lines which interconnect each respective data port with m different buffers such that the m different respective n-bit subsets of any given m-word data burst transmitted between a respective data port and said RAM are conducted to or from m different respective buffers.

Claim 26

The system of claim 20 wherein k=m.

Claim 29

The method of claim 20 wherein k=m.

Claim 30

The method of claim 20 wherein each data burst subset includes n bits.

Claim 31

The method of claim 20 and further including the step of: serially transferring respective data burst subsets of a respective data burst transmitted to or from any respective data port and the RAM between such respective data port and different storage elements in different buffers.

Claim 32

The method of claim 20 and further including the step of: serially transferring, one bit at a time, respective data burst subsets of a respective data burst in transit to or from any respective data port and the RAM between such respective data port and different storage elements in different buffers.

Claim 33

A multi-port memory system comprising: random access memory (RAM); k data ports; means for partitioning data bursts transferred through respective data ports into respective n-bit data burst subsets in which each respective subset includes n respective bits wherein such n respective bits occupy the same respective bit position in different data words of a respective data burst; m buffers means, each including k storage element mean for temporarily storing different data burst subsets of a respective data burst in transit to or from any respective data port and the RAM in different storage element means within different buffer means; and means for transferring all of the different data burst subsets of a respective data burst in transit to or from any respective data port and the RAM in parallel between different storage element means in different buffer means and the RAM.

Claim 34

A multi-port memory system comprising: random access memory (RAM); k data ports; means for partitioning data bursts transferred through respective data ports into respective n-bit data burst subsets in which each respective subset includes n respective bits wherein such n respective bits occupy the same respective bit position in different data words of a respective data burst; m buffers means, each including k storage element mean for temporarily storing different data burst subsets of a respective data burst in transit to or from any respective data port and the RAM in different storage element means within different buffer means; and means for transferring all of the different data burst subsets of a respective data burst in transit to or from any respective data port and the RAM in parallel between different storage element means in different buffer means and the RAM.

Claim 35

The method of claim 27 wherein k=m.

Claim 36

For use in a multi-port memory system which includes random access memory (RAM) and multiple data ports, a memory interface comprising: multiple buffers, each including multiple storage elements for simultaneous storage of multiple respective data burst subsets transitted between different respective data ports and said RAM; and an interconnect circuit which includes a multiplicity of data lines which interconnect each respective data port with multiple respective buffers such that different respective subsets of any given data burst transitted between a respective data port and said RAM are conducted to or from different respective buffers via different respective data lines.

Claim 37

For use in a multi-port memory system which includes random access memory (RAM) and multiple data ports, a memory interface comprising: multiple buffers, each including multiple storage elements for simultaneous storage of multiple respective data burst subsets transitted between different respective data ports and said RAM; and an interconnect circuit which includes a multiplicity of data lines which interconnect each respective data port with multiple respective buffers such that different respective subsets of any given data burst transitted between a respective data port and said RAM are conducted to or from different respective buffers via different respective data lines.

Claim 38

The system of claim 29, wherein respective buffers include parallel data path circuitry connectable between individual storage elements and said RAM; and wherein respective storage elements include serial transfer circuitry which serially transfers data burst subsets to and from said interconnect circuit.