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US4891795A Expired / Lapsed US ⏱️ 0.0 years remaining

Dual-port memory having pipelined serial output

Assignee: Texas Instruments Inc
•
Filing: 1989-04-07
•
Granted: 1990-01-02
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Expires: 2009-04-07
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Abstract

Abstract A dual-port memory which features a pipelined serial port is disclosed. The serial side of the dual-port memory contains a ripple counter which is broken between predetermined stages. The contents of the stages above the break are decoded to select a group of bits of the serial register for output, and the contents latched in a latch. In serial output, the contents of the stages below the break are decoded, so that responsive to the stages below the break reaching a certain value, the stages above the break are incremented and the incremented value decoded. Pass transistors between the register and the latch are turned off during such time as the incremented value is being decoded, so that the new value will not disturb the output. The latched output is selectively presented by a multiplexer which selects the latch bits responsive to the value of the stages below the break. Upon the value of the stages reaching its minimum value (i.e., the first bit of the next group), the pass transistors are enabled so that the contents corresponding to the incremented contents of the stages above the break are next presented at the output. Logic is provided so that during serial input the stages are not broken, to prevent the early incrementing of the counter prior to storage of the input data. Logic is also provided so that, initially after the counter is loaded with a new value, the first bits are output without being disturbed by an early incrementing of the counter stages above the break.

Inventors

  • 👤 Raymond Pinkham
  • 👤 Daniel F. Anderson

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-25 01:40
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1078; G11C7/109; G11C7/1015; G11C7/1039; G11C7/1075; G11C7/1087; G11C7/1093; G11C8/00; G11C8/16

Claims Analysis

Total Claims: 10
Claim 1
Independent Claim 165 words
A memory circuit of the type which stores binary data among a plurality of cell locations arranged in rows and columns, said circuit comprising: a data register into which the contents of a plurality of cell locations in a row are transferable and simultaneously storable among a plurality of register locations; counting means for sequentially selecting groups of register locations for outputting data from the register in groups, each data group corresponding to the contents of a group of register locations; a latch coupled to sequentially receive data groups from corresponding groups of register locations according to data selection with said counting means; intermediate data lines for effecting sequential transfer of data groups from the register to the latch; a multiplexer for serially outputting data stored in the latch; and circuitry for isolating a first of the groups of data when present on the intermediate data lines from the latch while a second of the groups of data is being serially output from the latch.
Claim 2
Dependent Claim 165 words
A memory circuit of the type which stores binary data among a plurality of cell locations arranged in rows and columns, said circuit comprising: a data register into which the contents of a plurality of cell locations in a row are transferable and simultaneously storable among a plurality of register locations; counting means for sequentially selecting groups of register locations for outputting data from the register in groups, each data group corresponding to the contents of a group of register locations; a latch coupled to sequentially receive data groups from corresponding groups of register locations according to data selection with said counting means; intermediate data lines for effecting sequential transfer of data groups from the register to the latch; a multiplexer for serially outputting data stored in the latch; and circuitry for isolating a first of the groups of data when present on the intermediate data lines from the latch while a second of the groups of data is being serially output from the latch.
Claim 3
Dependent Claim 30 words
The memory circuit of claim 1 wherein a portion of said counting means controls multiplexer operation for serial transfer of data stored in the latch according to a counting sequence.
Claim 4
Dependent Claim 20 words
The memory circuit of claim 2 wherein said counting means is responsive to a single serial clock signal for incrementing.
Claim 5
Dependent Claim 48 words
The memory circuit of claim 2 wherein said counting means comprises a single counter under the control of a single serial clock signal, said counter arranged into: a most significant portion for sequentially outputting data groups from the register; and a least significant portion for controlling multiplexer operation.
Claim 6
Dependent Claim 70 words
The memory circuit of claim 1 further including logic circuitry for selectively controlling the isolating circuitry to either; isolate the first of the groups of data when present on the intermediate data lines from the latch while the second of the groups of data is being serially output from the latch; or transfer the first of the groups of data when present on the intermediate data lines to the latch.
Claim 7
Dependent Claim 16 words
The memory circuit of claim 1 wherein each group of data includes four bits of information.
Claim 8
Dependent Claim 28 words
The memory circuit of claim 1 wherein each group of data includes four bits of information and the latch is capable of simultaneously storing four bits of data.
Claim 9
Dependent Claim 59 words
The memory circuit of claim 1 formed as a dual-port device with eight random access input/output lines and eight arrays of memory cells each organized into a plurality of rows and columns, said circuit comprising a data register for each array with each data register capable of simultaneously storing all of the data in a row of an array.
Claim 10
Dependent Claim 21 words
The circuit of claim 8 wherein each array includes 512 rows and 256 columns to provide one megabit of data storage.

References Cited (Backward Citations)

US4633441A Cited
US4817058A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1993-01-01 1993-07-03 1994-01-02 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1997-01-01 1997-07-03 1998-01-02 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2001-01-01 2001-07-03 2002-01-02 $7700.00 Window Closed / Lapsed

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