US4750154A
Expired / Lapsed
US
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Memory alignment system and method
Assignee: CVSI Inc
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Filing: 1984-07-10
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Granted: 1988-06-07
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Expires: 2004-07-10
Abstract
Abstract A memory alignment system and method are disclosed having a memory bus designed to accommodate more than one write instruction at a time and where data from different write instructions are merged together when the writes are destined for alignable locations in memory. In one embodiment, a write buffer and a comparator are configured to compare successive instructions for alignable destination addresses. In another embodiment, a content associative buffer is employed to compare the address of a write instruction with the addresses of all other stored write instructions. A variable scheduler to control the unloading of the buffer is also disclosed as is an apparatus for merging data read from memory with data awaiting transmission to memory to obtain the most up-to-date version.
Inventors
- 👤 Brian Lefsky
- 👤 Paul K. Rodman
- 👤 Stephen S. Corbin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 22:12
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/30003; G06F9/3004; G06F9/30043; G06F13/00; G06F13/14; G06F13/16; G06F13/1605; G06F13/161; G06F13/1626; G06F13/1631; G06F13/38; G06F13/42; G06F13/4204; G06F13/4234; G06F5/00; G06F5/06; G06F5/065; G06F9/30181; G06F9/38; G06F9/3824; G06F9/3826
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
265 words
A memory alignment system for use in a digital data memory storage system having a central processor capable of operating on data words of at least one defined width, a memory having a plurality of locations having defined addresses, the widths of said locations corresponding to the defined widths of said data words, and the addresses further grouped into lines, each line having at least two data locations, and a memory writing means responsive to write instructions from the processor for transmitting data words from said processor to said memory, the writing means being capable of transmitting into said memory of at least two data words together when destined for the same line, the improvement wherein the memory alignment system comprises: A. a write buffer means connected to the processor and the writing means, the buffer means having a plurality of rows, each row having a plurality of locations for receiving and storing data words destined for alignable locations in said memory, in association with their memory addresses, B. comparator means for comparing a first address of a data word previously stored in said buffer means with a second address contained in a write instruction, and C. routing means responsive to said comparator means for routing said data word associated with said write instruction to the same row of said write buffer as said previously stored data word when said first and second addresses are located in the line of memory, thereby enabling the writing means to transfer in a single memory write cycle at least two data words to the same line of memory.
Claim 2
Dependent Claim
265 words
A memory alignment system for use in a digital data memory storage system having a central processor capable of operating on data words of at least one defined width, a memory having a plurality of locations having defined addresses, the widths of said locations corresponding to the defined widths of said data words, and the addresses further grouped into lines, each line having at least two data locations, and a memory writing means responsive to write instructions from the processor for transmitting data words from said processor to said memory, the writing means being capable of transmitting into said memory of at least two data words together when destined for the same line, the improvement wherein the memory alignment system comprises: A. a write buffer means connected to the processor and the writing means, the buffer means having a plurality of rows, each row having a plurality of locations for receiving and storing data words destined for alignable locations in said memory, in association with their memory addresses, B. comparator means for comparing a first address of a data word previously stored in said buffer means with a second address contained in a write instruction, and C. routing means responsive to said comparator means for routing said data word associated with said write instruction to the same row of said write buffer as said previously stored data word when said first and second addresses are located in the line of memory, thereby enabling the writing means to transfer in a single memory write cycle at least two data words to the same line of memory.
Claim 3
Dependent Claim
20 words
The alignment system of claim 1 wherein the comparator means further comprises means for comparing addresses of successive write instructions.
Claim 4
Dependent Claim
36 words
The alignment system of claim 1 wherein the compartor means further comprises means for comparing an address of each write instruction with the addresses of a plurality of write instructions already stored in the buffer means.
Claim 5
Dependent Claim
69 words
The alignment system of claim 1 wherein the buffer means comprises: I. a data store having a plurality of rows for storing data portions of each write instruction; II. an address store for storing a memory address associated with each write instruction; and III. a control store associated with each row of said data store for indicating the presence and the width of write instruction stored in said row.
Claim 6
Dependent Claim
37 words
The alignment system of claim 1 wherein the defined width of the data words is 16-bits and the routing means further comprises means for routing two 16-bit data words to the same row of said write buffer.
Claim 7
Dependent Claim
37 words
The alignment system of claim 1 wherein the defined width of the data words is 32-bits and the routing means further comprises means for, routing two 32-bit data words to the same row of said write buffer.
Claim 8
Dependent Claim
44 words
The alignment system of claim 1 wherein the central processor is capable of operating on data words of both 16-bit and 32-bit widths and the routing means further comprises means for routing a plurality of 16-bit data words, 32-bit data words and combinations thereof.
Claim 9
Dependent Claim
27 words
The alignment system of claim 1 wherein the memory writing means further comprises a variable operation scheduling means for scheduling the transfer of write instructions to memory.
Claim 10
Dependent Claim
30 words
The alignment system of claim 1 wherein the write buffer means further comprises a content associative memory including an address store containing a memory address for each stored data word.
Claim 11
Dependent Claim
77 words
The alignment system of claim 1 wherein the system further comprises read processing means for processing instructions to read data addressed locations in the write buffer means, the read processing means comprising means for comparing an address of a read instruction with addresses of pending data words stored in the buffer means, and means responsive to the comparing means for substituting when a match is found, data sotred in the buffer for data read from the memory.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-06-07 | 1991-12-07 | 1992-06-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-06-07 | 1995-12-07 | 1996-06-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-06-07 | 1999-12-07 | 2000-06-07 | $7700.00 | Window Closed / Lapsed |