US4388701A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Recirculating loop memory array having a shift register buffer for parallel fetching and storing
Assignee: International Business Machines Corp
•
Filing: 1980-09-30
•
Granted: 1983-06-14
•
Expires: 2000-09-30
Abstract
Abstract A recirculating loop memory array is disclosed adapted for the parallel as well as serial fetching and storing of data while requiring only a single input and single output data terminal. Each loop of the array is provided with a shift register stage for parallel data accessing. A particular recirculating bit in all of the loops can be fetched in parallel into their respective shift register stages and, conversely, the bits stored in the shift register stages can be loaded in parallel into predetermined recirculating bits of their respective loops. The shift register is operated at high speed so that it may be completely loaded or unloaded during the interval between successive steppings of the loops.
Inventors
- 👤 Frederick J. Aichelmann, Jr.
- 👤 Fernando Neves
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 12:01
CPC Classifications
G; G11; G11C; G11C19/00; G11C19/28; G11C19/287; G11C19/282; G11C19/285
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
149 words
A memory array comprising, a plurality of recirculating loop memory elements, said elements being clocked in synchronism so that the corresponding bits recirculate in their respective loops with the same time phase, a shift register having a serial data input and a serial data output and comprising a number of cells equal in number to the number of said elements a data input line coupled to said input, a data output line coupled to said output, first means for selectively connecting each said coil to a respective one of said elements for writing data from said cells into said elements, second means for selectively connecting each said cell to a respective one of said elements for reading data from said elements into said cells, and means for shifting data stored in said shift register throughout said number of cells in the time interval between successive clockings of said elements.
Claim 2
Dependent Claim
149 words
A memory array comprising, a plurality of recirculating loop memory elements, said elements being clocked in synchronism so that the corresponding bits recirculate in their respective loops with the same time phase, a shift register having a serial data input and a serial data output and comprising a number of cells equal in number to the number of said elements a data input line coupled to said input, a data output line coupled to said output, first means for selectively connecting each said coil to a respective one of said elements for writing data from said cells into said elements, second means for selectively connecting each said cell to a respective one of said elements for reading data from said elements into said cells, and means for shifting data stored in said shift register throughout said number of cells in the time interval between successive clockings of said elements.
Claim 3
Dependent Claim
13 words
The apparatus defined in claim 1 wherein said elements are charge coupled devices.
Claim 4
Dependent Claim
22 words
The apparatus defined in claim 1 and further including third means independent of said shift register for writing data into said elements.
Claim 5
Dependent Claim
18 words
The apparatus defined in claim 3 and further including means for operating said first and third means alternatively.
Claim 6
Dependent Claim
22 words
The apparatus defined in claim 1 and further including fourth means independent of said shift register for reading data from said elements.
Claim 7
Dependent Claim
18 words
The apparatus defined in claim 5 and further including means for operating said second and fourth means alternatively.
References Cited (Backward Citations)
US3760382A
Cited
US3761695A
Cited
US3783254A
Cited
US3784907A
Cited
US4128879A
Cited
JPS5321541A
Cited
US4321694A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-06-13 | 1986-12-13 | 1987-06-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-06-13 | 1990-12-13 | 1991-06-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-06-13 | 1994-12-13 | 1995-06-14 | $7700.00 | Window Closed / Lapsed |