US5835925A — Using external registers to extend memory referen…

Claim 1

Independent Claim 167 words

An external circuit for use in accessing a memory location within a system having a processor and a plurality of memory locations separate from the processor, wherein the plurality of memory locations includes a first memory location, the circuit comprising: an address bus; a data bus; a plurality of external registers, including a first external register, connected to the data bus, wherein each of the plurality of external registers responds to an address written on the address bus to store data written by the processor on the data bus; address translation means, connected to the address bus and to the data bus, for calculating, based on an index written to the data bus, an address associated with the first memory location; and transfer means, connected to the plurality of external registers, for transferring data between the first memory location and the first external register, wherein the transfer means includes means for supporting references to two or more of the plurality of memory locations at the same time.

Claim 2

Dependent Claim 167 words

An external circuit for use in accessing a memory location within a system having a processor and a plurality of memory locations separate from the processor, wherein the plurality of memory locations includes a first memory location, the circuit comprising: an address bus; a data bus; a plurality of external registers, including a first external register, connected to the data bus, wherein each of the plurality of external registers responds to an address written on the address bus to store data written by the processor on the data bus; address translation means, connected to the address bus and to the data bus, for calculating, based on an index written to the data bus, an address associated with the first memory location; and transfer means, connected to the plurality of external registers, for transferring data between the first memory location and the first external register, wherein the transfer means includes means for supporting references to two or more of the plurality of memory locations at the same time.

Claim 3

Dependent Claim 21 words

The circuit according to claim 1 wherein the means for supporting references includes means for permitting out of sequence memory returns.

Claim 4

Dependent Claim 57 words

The circuit according to claim 1 wherein the means for supporting references includes means for reading a state code associated with each of the plurality of external registers, wherein the state code associated with the first external register indicates whether the transfer of data between the first memory location and the first external register has completed correctly.

Claim 5

Dependent Claim 18 words

The circuit according to claim 3, wherein the state codes are stored in a dual-ported random access memory.

Claim 6

Dependent Claim 28 words

The circuit according to claim 1 wherein the address translation means includes a remote translation buffer (RTB) used to convert a system virtual address to a physical address.

Claim 7

Dependent Claim 54 words

The circuit according to claim 1 wherein the address translation means includes an external register request queue used to store external register block write requests, wherein the external register request queue includes a plurality of queue entries, wherein each queue entry includes storage for a command, an external register pointer and a data argument.

Claim 8

Independent Claim 124 words

A method of extending the address space of a microprocessor having an external data path, the method comprising the steps of: providing a plurality of external registers, including a first external register; defining a register operation data word having an index field; writing an index into the index field; and executing a memory instruction, wherein the step of executing the memory instruction includes the steps of: writing the register operation data word to an address associated with the first external register, wherein the step of writing includes the step of placing the register operation data word on said external data path; calculating, based on the index, an address for a memory location; and transferring data between the memory location and the first external register.

Claim 9

Independent Claim 124 words

A method of extending the address space of a microprocessor having an external data path, the method comprising the steps of: providing a plurality of external registers, including a first external register; defining a register operation data word having an index field; writing an index into the index field; and executing a memory instruction, wherein the step of executing the memory instruction includes the steps of: writing the register operation data word to an address associated with the first external register, wherein the step of writing includes the step of placing the register operation data word on said external data path; calculating, based on the index, an address for a memory location; and transferring data between the memory location and the first external register.

Claim 10

Dependent Claim 101 words

The method according to claim 7 wherein the plurality of external registers further includes a second external register and wherein the step of providing further comprises the steps of: storing a base address offset in the second external register; and wherein the step of calculating an address for a memory location comprises the steps of: reading the base address offset stored in the second register; calculating an offset value as a function of the index; calculating a virtual address as a function of the offset value and the base address offset; and extracting a processor element number from the virtual address.

Claim 11

Dependent Claim 47 words

The method according to claim 8 wherein the register operation data word further includes a Mask/Offset/Operand block (MOB) pointer field and wherein the step of reading the base address includes the step of using the contents of the MOB pointer field to access said second external register.

Claim 12

Dependent Claim 51 words

The method according to claim 8 wherein the plurality of external registers further includes a third external register and wherein the step of extracting includes the steps of: storing a centrifuge mask in the third external register; and applying the centrifuge mask to the virtual address to obtain the processor number.

Claim 13

Independent Claim 186 words

A method of executing atomic operations in a system having a microprocessor, wherein the microprocessor includes an external data path, the method comprising the steps of: providing a plurality of external registers, including a first external register; defining a register operation data word having an index field; writing an index into the index field; storing a first operand into said first external register; and executing an atomic operation instruction, wherein the step of executing the atomic operation instruction includes the steps of: writing the register operation data word to an address associated with the first external register, wherein the step of writing includes the step of placing the register operation data word on said external data path; calculating, based on the index, an address for a memory location; and performing an indivisible read-modify-write operation on data stored in the memory location, wherein the step of performing an indivisible read-modify-write operation includes the steps of: a) reading the memory location to obtain a second operand; b) calculating a result as a function of the first and second operands; and c) storing the result in said memory location.

Claim 14

Independent Claim 186 words

A method of executing atomic operations in a system having a microprocessor, wherein the microprocessor includes an external data path, the method comprising the steps of: providing a plurality of external registers, including a first external register; defining a register operation data word having an index field; writing an index into the index field; storing a first operand into said first external register; and executing an atomic operation instruction, wherein the step of executing the atomic operation instruction includes the steps of: writing the register operation data word to an address associated with the first external register, wherein the step of writing includes the step of placing the register operation data word on said external data path; calculating, based on the index, an address for a memory location; and performing an indivisible read-modify-write operation on data stored in the memory location, wherein the step of performing an indivisible read-modify-write operation includes the steps of: a) reading the memory location to obtain a second operand; b) calculating a result as a function of the first and second operands; and c) storing the result in said memory location.

Claim 15

Dependent Claim 26 words

The method according to claim 11 wherein the step of calculating a result includes the step of writing the second operand into the first external register.

Claim 16

Dependent Claim 94 words

The method according to claim 11 wherein the plurality of external registers further includes a second external register, wherein the method further comprises the step of storing a base address offset in the second external register; and wherein the step of calculating an address comprises the steps of: reading the base address offset stored in the second register; calculating an offset value as a function of the index; calculating a virtual address as a function of the offset value and the base address offset; and extracting a processor element number from the virtual address.

Claim 17

Dependent Claim 44 words

The method according to claim 13 wherein the register operation data word further includes a (Mask/Offset/Operand block) (MOB) pointer field containing a pointer and wherein the step of reading the base address includes the step of accessing said second external register via said pointer.

Claim 18

Dependent Claim 51 words

The method according to claim 13 wherein the plurality of external registers further includes a third external register and wherein the step of extracting includes the steps of: storing a centrifuge mask in the third external register; and applying the centrifuge mask to the virtual address to obtain the processor number.

Claim 19

Dependent Claim 138 words

The method according to claim 11 wherein the step of providing a plurality of external registers includes the steps of: providing a plurality of remote processing elements connected to the microprocessor over an interconnect network; and distributing the plurality of external registers so that each of the plurality of remote processing elements includes one external register from said plurality of external registers; wherein the step of calculating an address for a memory location includes the step of determining the remote processing element associated with the memory location; and wherein the step of reading the memory location includes the steps of: forming a memory request packet, wherein the memory request packet includes the first operand and an address corresponding to the memory location; and sending the memory request packet to the remote processing element associated with the memory location.

Claim 20

Dependent Claim 121 words

In a system including a microprocessor having an instruction set and an external data path, a method of extending the instruction set, the method comprising the steps of: providing a plurality of external registers, including first, second and third external registers; defining a register operation data word; and executing an extended instruction, wherein the step of executing the extended operation instruction includes the steps of: writing the register operation data word to an address associated with the first external register, wherein the step of writing includes the step of placing the register operation data word on said external data path; calculating a result as a function of the register operation data word; and storing the result in said first external register.

Claim 21

Dependent Claim 121 words

In a system including a microprocessor having an instruction set and an external data path, a method of extending the instruction set, the method comprising the steps of: providing a plurality of external registers, including first, second and third external registers; defining a register operation data word; and executing an extended instruction, wherein the step of executing the extended operation instruction includes the steps of: writing the register operation data word to an address associated with the first external register, wherein the step of writing includes the step of placing the register operation data word on said external data path; calculating a result as a function of the register operation data word; and storing the result in said first external register.

Claim 22

Dependent Claim 51 words

The method according to claim 17, wherein the register operation data word includes a Mask/Offset/Operand block MOB) pointer and wherein the step of calculating includes the steps of: using the MOB pointer to read an operand from the second external register; and calculating the result as a function of the operand.

Claim 23

Dependent Claim 84 words

The method according to claim 17, wherein the register operation data word includes a Mask/Offset/Operand block (MOB) pointer and an index and wherein the step of calculating includes the steps of: using the MOB pointer to read a centrifuge mask from the second external register; using the MOB pointer to read a base address offset from the third external register; and calculating a processing element number and a memory offset as a function of the index, the base address offset and the centrifuge mask.

Claim 24

Independent Claim 148 words

A method of executing an external register instruction, the method comprising the steps of: providing a plurality of external registers; defining a Mask/Offset/Operand block (MOB) pointer which points to an aligned block of arguments stored in the plurality of external registers; defining an external register operation data word, wherein the external register operation data word includes an index field and an MOB pointer field; storing an argument data word in the aligned block of arguments; writing the MOB pointer into the MOB pointer field; and writing the external register operation data word to an external address, wherein the step of writing includes the steps of: decoding the external address to determine the external register instruction; extracting the MOB pointer from the MOB pointer field; accessing the aligned block of arguments to obtain the argument data word; and calculating a result as a function of the argument data word.

Claim 25

Independent Claim 148 words

A method of executing an external register instruction, the method comprising the steps of: providing a plurality of external registers; defining a Mask/Offset/Operand block (MOB) pointer which points to an aligned block of arguments stored in the plurality of external registers; defining an external register operation data word, wherein the external register operation data word includes an index field and an MOB pointer field; storing an argument data word in the aligned block of arguments; writing the MOB pointer into the MOB pointer field; and writing the external register operation data word to an external address, wherein the step of writing includes the steps of: decoding the external address to determine the external register instruction; extracting the MOB pointer from the MOB pointer field; accessing the aligned block of arguments to obtain the argument data word; and calculating a result as a function of the argument data word.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	2001-11-09	2002-05-11	2002-11-10	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2005-11-09	2006-05-11	2006-11-10	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2009-11-09	2010-05-11	2010-11-10	$7700.00	Window Closed / Lapsed

Using external registers to extend memory reference capabilities of a microprocessor

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