US5627986A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Device and method for selecting and addressing extended memory addresses
Assignee: Mindspeed Technologies LLC
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Filing: 1994-12-08
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Granted: 1997-05-06
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Expires: 2014-12-08
Abstract
Abstract An extended memory mapping and selecting scheme for a microprocessor structured with multiple internal address lines. The internal address lines are coupled to external memory devices via a dual port RAM which enables the addresses of the external memories to be mapped and translated into the internal address lines for access by the microprocessor. The memory addressing capability is effectively enhanced by allowing the limited number of internal address lines to address larger external memories having a greater number of address locations.
Inventors
- 👤 Robert W. Frankland
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 19:55
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/06; G06F12/0615; G06F12/0623; G06F12/0223; G06F12/0292
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
292 words
A memory address mapping and access speed selection apparatus for accessing a plurality of external memories with an internal address of a microprocessor, the apparatus comprising: X external address lines connected to the plurality of external memories; a chip select line connected to each external memory, said chip select line selecting which memory will be addressed during a particular access; Y internal address lines connected to a microprocessor; Z data lines connected to the microprocessor and each of the plurality of extended memories; a dual-port random access memory (DPRAM) having a write port and a read port; said write port having inputs connected to M of the internal address lines, where M is less than Y, said write port further connected to the Z data lines from the microprocessor, wherein the microprocessor inputs data during a programming mode over the Z data lines into the dual-port random access memory at dual-port random access memory addresses indicated by the M internal address lines, wherein the data input into the dual-port random access memory addresses includes high order address bits of an external memory, address and a chip select value indicating a particular one of the plurality of external memories; said read port having outputs connected to N of the external address lines, where N is less than X, said read port outputting high order address bits and a particular chip select signal of a particular external memory when an internal address value is input to the write port over the M internal address lines during a non-programming access; and wherein the particular chip select value output by the read port of the dual-port random access memory during a non-programming access is utilized in selecting the speed of access to the particular external memory.
Claim 2
Dependent Claim
292 words
A memory address mapping and access speed selection apparatus for accessing a plurality of external memories with an internal address of a microprocessor, the apparatus comprising: X external address lines connected to the plurality of external memories; a chip select line connected to each external memory, said chip select line selecting which memory will be addressed during a particular access; Y internal address lines connected to a microprocessor; Z data lines connected to the microprocessor and each of the plurality of extended memories; a dual-port random access memory (DPRAM) having a write port and a read port; said write port having inputs connected to M of the internal address lines, where M is less than Y, said write port further connected to the Z data lines from the microprocessor, wherein the microprocessor inputs data during a programming mode over the Z data lines into the dual-port random access memory at dual-port random access memory addresses indicated by the M internal address lines, wherein the data input into the dual-port random access memory addresses includes high order address bits of an external memory, address and a chip select value indicating a particular one of the plurality of external memories; said read port having outputs connected to N of the external address lines, where N is less than X, said read port outputting high order address bits and a particular chip select signal of a particular external memory when an internal address value is input to the write port over the M internal address lines during a non-programming access; and wherein the particular chip select value output by the read port of the dual-port random access memory during a non-programming access is utilized in selecting the speed of access to the particular external memory.
Claim 3
Dependent Claim
33 words
The memory address mapping and access speed selection apparatus of claim 1, further comprising: means for initializing the dual-port random access memory addresses, upon the power on/reset of the microprocessor, to predetermined values.
Claim 4
Dependent Claim
16 words
The memory, address mapping and access speed selection apparatus of claim 1, wherein M equals 3.
Claim 5
Independent Claim
249 words
A method of memory address mapping and access speed selection for accessing a plurality of external memories with an internal address of a microprocessor the method comprising: programming a write port of a dual-port random access memory (DPRAM) having inputs connected to M internal address lines of the microprocessor, said microprocessor having Y internal address lines and where M is less than Y, said write port further connected to Z data lines from the microprocessor, wherein the microprocessor inputs data during a programming mode over the Z data lines into the dual-port random access memory at addresses indicated by the M internal address lines, the data input into the dual-port random access memory addresses including high order address bits of an external memory address and a chip select value indicating a particular one of the plurality of external memories; accessing a read port during a non-programming mode, said read port having outputs connected to N external address lines of the external memories, each external memory having a total of X address lines where N is less than Y, said read port outputting high order address bits and a particular chip select value of a particular external memory when an internal address value is input to the write port over the M internal address lines during the access; and selecting a speed of access to the particular external memory based on the particular chip select value output by the read port of the dual-port random access memory during the access.
Claim 6
Independent Claim
249 words
A method of memory address mapping and access speed selection for accessing a plurality of external memories with an internal address of a microprocessor the method comprising: programming a write port of a dual-port random access memory (DPRAM) having inputs connected to M internal address lines of the microprocessor, said microprocessor having Y internal address lines and where M is less than Y, said write port further connected to Z data lines from the microprocessor, wherein the microprocessor inputs data during a programming mode over the Z data lines into the dual-port random access memory at addresses indicated by the M internal address lines, the data input into the dual-port random access memory addresses including high order address bits of an external memory address and a chip select value indicating a particular one of the plurality of external memories; accessing a read port during a non-programming mode, said read port having outputs connected to N external address lines of the external memories, each external memory having a total of X address lines where N is less than Y, said read port outputting high order address bits and a particular chip select value of a particular external memory when an internal address value is input to the write port over the M internal address lines during the access; and selecting a speed of access to the particular external memory based on the particular chip select value output by the read port of the dual-port random access memory during the access.
Claim 7
Dependent Claim
32 words
The method of memory address mapping and access speed selection of claim 4, further comprising the step of: initializing the dual-port random access memory addresses to predetermined values upon microprocessor power on/reset.
Claim 8
Dependent Claim
16 words
The memory address mapping and access speed selection method of claim 4, wherein M equals 3.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-05-05 | 2000-11-04 | 2001-05-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-05-05 | 2004-11-04 | 2005-05-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-05-05 | 2008-11-04 | 2009-05-06 | $7700.00 | Window Closed / Lapsed |