Consistency ensuring system for the contents of a cache memory

Claim 1

A consistency ensuring system having at least one main memory and a plurality of processors, each of said plurality of processors having a corresponding instruction cache memory and a corresponding operand cache memory wherein each of said plural processors comprises: flush address array means for keeping a copy of an address array to be looked up and for invalidating a block of data in the corresponding instruction cache memory or the corresponding operand cache memory in response to storing a corresponding block of data into said main memory from a non-corresponding processor; address converting means for converting a virtual address to a real address and for updating a page table word after address conversion resulting in an updated page table word and storing the updated page table word in said main memory and not in said corresponding instruction cache memory and said corresponding operand cache memory; signal generating means for generating a page table word store notice signal when said address converting means stores said updated page table word into said main memory; and flush address array invalidating means for looking up and invalidating, in response to said page table word store notice signal and a real memory address of said page table word from said corresponding processor, the corresponding block of data in the corresponding instruction cache memory and the corresponding operand cache memory of said corresponding processor, wherein whenever an instruction is stored in the corresponding instruction cache memory and the main memory, said instruction cannot be stored in the corresponding operand cache memory and, whenever an operand is stored in the corresponding operand cache memory and the main memory, said operand cannot be stored in the corresponding instruction cache memory.