Synchronized semiconductor memory

Claim 1

A synchronized semiconductor memory device comprising: a memory cell array constituting the dynamic random access memory; address input means receiving an external address signal containing a row address/column address; address set means receiving an address information from the address input means and for generating and outputting a memory selecting signal to said memory cell array; command input means receiving an external command signal containing a row address selection control/reading control/writing control; data reading/writing control means receiving a command information from the command input means, and for controlling a data read operation and a data writing operation to the memory cell array; data output means controlled by the data reading/writing control means and for outputting the data read from the memory cell array; data input means controlled by the data reading/writing control means and for receiving the data to written into said memory cell array; clock input means receiving an external clock signal; and internal clock generating means receiving a clock information from the clock input means, and for generating a predetermined reference internal clock; and internal clock timing control means receiving the predetermined reference internal clock, and for generating a plurality of internal clock signals having different timings for the address input means, the address set means, the command input means, the data reading/writing control means, the data output means and the data input means; wherein the clock input means comprising first and the second clock input means; and wherein the internal clock generating means comprising a first internal clock generating means receiving a clock information from the first clock input means, for generating a fist reference internal clock signal controlling the address input means, the address set means, the command input means, the data reading/writing control means, the data output means and the data input means, a second internal clock generating means receiving the clock information through the second clock input means, for generating a second reference internal clock signal controlling only the data output means, and a logic circuit means receiving the first reference internal clock signal outputted from the first internal clock generate means, a specific internal clock enable signal outputted from the data reading/writing control means, a read command signal outputted from the command input means and a level signal set in accordance with a given mode register cycle, the logic circuit means generating a power supply signal for controlling the supply or no supply of power to the second clock input means.