US5335206A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor storage device
Assignee: Fujitsu VLSI Ltd
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Filing: 1990-11-07
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Granted: 1994-08-02
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Expires: 2010-11-07
Abstract
Abstract The present invention relates to a semiconductor storage device for executing an address multiplex method. An object of the invention is to provide a semiconductor storage device capable of higher access speed, and the semiconductor storage device includes a first timing circuit (1) for detecting a time at which a row address strobe signal is inactivated and for outputting a first timing signal; a second timing circuit (1) for detecting a time change from the inactive state to the active state of the row address strobe signal and for outputting a second timing signal; an address change detection circuit (5) for detecting a change of content of a row address signal between the first timing signal and the second timing signal and for outputting an address change signal; a row decoder (13) for decoding the content of the row address signal in accordance with the first timing signal, and when the address change signal is output, for decoding the content of the row address signal in accordance with the second timing signal; and a word line driver (14) for activating the decoded word line in accordance with the second timing signal; and is applied to a random access memory.
Inventors
- 👤 Satoru Kawamoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 00:21
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/4076; G11C8/00; G11C8/18
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
154 words
A semiconductor storage device, comprising: a first timing circuit for generating a first timing signal in response to inactivation of a row address strobe signal; a second timing circuit for generating a second timing signal in response to activation of the row address strobe signal after the inactivation of a row address strobe signal; an address change detection circuit for generating an address change detection signal in response to a change of the row address which has occurred during a period between the inactivation and activation of the row address signal; a row decoder decoding a row address for subsequent access in response to the first timing signal and simultaneously decoding a changed row address signal in response to the second timing signal when the address change detection signal is generated; and a word driver, connected to the row decoder, selecting a word line and being activated in response to the second timing signal.
Claim 2
Dependent Claim
154 words
A semiconductor storage device, comprising: a first timing circuit for generating a first timing signal in response to inactivation of a row address strobe signal; a second timing circuit for generating a second timing signal in response to activation of the row address strobe signal after the inactivation of a row address strobe signal; an address change detection circuit for generating an address change detection signal in response to a change of the row address which has occurred during a period between the inactivation and activation of the row address signal; a row decoder decoding a row address for subsequent access in response to the first timing signal and simultaneously decoding a changed row address signal in response to the second timing signal when the address change detection signal is generated; and a word driver, connected to the row decoder, selecting a word line and being activated in response to the second timing signal.
Claim 3
Dependent Claim
66 words
A semiconductor storage device as set forth in claim 1, wherein the address change detection circuit is a row address transition detector which receives a complementary address signal, monitors the content of the row address signal, compares the contents of the row address signal during the rising or falling times of the row address strobe signal, and outputs the address change signal when the content changes.
Claim 4
Dependent Claim
32 words
A semiconductor storage device as set forth in claim 1, wherein said second timing signal is formed by a falling edge of the row address strobe signal and the address change signal.
Claim 5
Dependent Claim
99 words
A data access method of a semiconductor storage device, comprising the steps of: decoding a content of a row address signal during a term from inactivation to activation of a row address strobe signal, and simultaneously when the above address signal, change is outputted, decoding the content of the row address signal in accordance with a first timing signal; activating a word line in accordance with an input of the decoded signal after the row address strobe signal is activated; and then, in accordance with an input of a column address signal, obtaining information of one arbitrary memory cell.
Claim 6
Dependent Claim
99 words
A data access method of a semiconductor storage device, comprising the steps of: decoding a content of a row address signal during a term from inactivation to activation of a row address strobe signal, and simultaneously when the above address signal, change is outputted, decoding the content of the row address signal in accordance with a first timing signal; activating a word line in accordance with an input of the decoded signal after the row address strobe signal is activated; and then, in accordance with an input of a column address signal, obtaining information of one arbitrary memory cell.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-08-01 | 1998-01-31 | 1998-08-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-08-01 | 2002-01-31 | 2002-08-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-08-01 | 2006-01-31 | 2006-08-02 | $7700.00 | Window Closed / Lapsed |