EP0182457A2
Expired / Lapsed
EP
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A dynamic random access memory circuit and a method of stabilizing current surges in such a memory circuit
Assignee: Thorn EMI North America Inc
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Filing: 1985-08-15
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Granted: —
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Expires: 2005-08-15
Abstract
Abstract A dynamic random access memory circuit and a method of stabilizing current surges in such a memory circuit are provided. Peak current through each sense amplifier (Fig. 1) is stabilized through initiation of the sense and restore operations during the chip active period and completion of the sense and restore operation during the chip precharge period. The delay between first and second sensing signals (Ø s1 , 0 52 ) is controlled to be longer for those temperature and power supply conditions under which the chip is operating fastest. Correspondingly, the delay between first and second sensing signals is made shorter for those temperature and power supply conditions under which the chip is operating slowest. Overall peak current is limited to that drawn through small transistors used to begin turning on the sense amplifier. The duration of the second sensing signal is responsive to the temperature and power supply variation so it endures for an acceptable period in which to complete the sense and restore function. The second sensing signal timing is not determined by the first sensing signal.
Inventors
- 👤 James D. Allan
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 04:12
CPC Classifications
G; G05; G05F; G05F1/00; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/4076
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
47 words
A method for stabilizing current surges during sense and restore operations of a dynamic random access memory circuit having active and precharge periods, the method comprising initiating the sense and restore operation during the active period; and completing the sense and restore operation during the precharge period.
Claim 2
Independent Claim
47 words
A method for stabilizing current surges during sense and restore operations of a dynamic random access memory circuit having active and precharge periods, the method comprising initiating the sense and restore operation during the active period; and completing the sense and restore operation during the precharge period.
Claim 3
Independent Claim
59 words
A method for stabilizing current surges during sense and restore operations of a dynamic random access memory circuit having active and precharge periods, the method comprising: generating a first sensing signal in response to the initiation of the active period after a predetermined delay; and generating a final sensing signal in response to the completion of the active period.
Claim 4
Independent Claim
59 words
A method for stabilizing current surges during sense and restore operations of a dynamic random access memory circuit having active and precharge periods, the method comprising: generating a first sensing signal in response to the initiation of the active period after a predetermined delay; and generating a final sensing signal in response to the completion of the active period.
Claim 5
Dependent Claim
21 words
A method as claimed in Claim 2 further comprising terminating the first and second sensing signals after a second time delay.
Claim 6
Dependent Claim
17 words
A method as claimed in Claim 3, wherein said second time delay is determinable by on-chip circuitry.
Claim 7
Independent Claim
33 words
A method as claimed in any of Claims 2 to 4, wherein said predetermined delay comprises a time approximately equal to the time required to set up the bit lines on the chip.
Claim 8
Dependent Claim
61 words
A dynamic random access memory circuit having active and precharge periods and having means for stabilizing current surges, said stabilization means comprising: first logic means responsive to the initiation of the active period to generate a first sensing signal after a first delay; and second logic means responsive to the completion of the active period to generate a second sensing signal.
Claim 9
Dependent Claim
61 words
A dynamic random access memory circuit having active and precharge periods and having means for stabilizing current surges, said stabilization means comprising: first logic means responsive to the initiation of the active period to generate a first sensing signal after a first delay; and second logic means responsive to the completion of the active period to generate a second sensing signal.
Claim 10
Dependent Claim
28 words
A DRAM circuit as claimed in Claim 6, wherein said first time delay is representational of the time required to set up the chip bit lines for sensing.
Claim 11
Dependent Claim
32 words
A DRAM circuit as claimed in Claim 6 or 7, further comprising: third logic means responsive to the completion of the active period to terminate said sensing signals after a second delay.
Claim 12
Dependent Claim
30 words
A DRAM circuit as claimed in Claim 8, wherein said third logic means is responsive to the initiation of the active period to enable said first and second logic means.
Claim 13
Dependent Claim
24 words
A DRAM circuit as claimed in Claim 8 or 9, in which said second time delay is determined by a series of MOS inverters.
Claim 14
Dependent Claim
102 words
A dynamic random access memory circuit having chip active and precharge periods and having means for compensating for ambient environment variations to control current surges in said circuit, said compensation means comprising: control means responsive to the initiation of the active period to generate an enabling signal; first generating means coupled to receive said enabling signal and responsive to the initiation of said active period to generate a first sensing signal after an ambient environment variable delay; and second generating means coupled to receive said enabling signal in response to the termination of said active period to generate a second sensing signal.
Claim 15
Dependent Claim
102 words
A dynamic random access memory circuit having chip active and precharge periods and having means for compensating for ambient environment variations to control current surges in said circuit, said compensation means comprising: control means responsive to the initiation of the active period to generate an enabling signal; first generating means coupled to receive said enabling signal and responsive to the initiation of said active period to generate a first sensing signal after an ambient environment variable delay; and second generating means coupled to receive said enabling signal in response to the termination of said active period to generate a second sensing signal.
Claim 16
Dependent Claim
68 words
A DRAM circuit as claimed in Claim 11 further comprising: timing means responsive to the termination of said active period and responsively coupled to said control means for causing said control means to generate a disabling signal to disable said first and second generating means at a preselected delay after the active period termination, whereby the duration of said second sensing signal is determined by said preselected delay.
Claim 17
Dependent Claim
47 words
A DRAM circuit as claimed in any of Claims 6 to 12, said circuit further comprising: a sense amplifier having first and second paired inputs adapted to receive said first and second sensing signals and the logical complements of said sensing signals to drive said sense amplifier.
Claim 18
Dependent Claim
57 words
A DRAM circuit as claimed in Claim 13, wherein said first paired inputs are coupled to the gates of a first pair of transistors and said second paired inputs are coupled to the gates of a second pair of transistors and wherein said second pair of transistors are substantially larger devices than said first pair of transistors.
Claim 19
Independent Claim
134 words
A method for compensating for temperature and power supply variations in a dynamic random access memory circuit to control current surges in said memory circuit, said method comprising: sensing a first row address strobe signal transition to indicate that the chip has entered an active period; generating a preliminary sensing signal in response to said first row address strobe signal transition after a first temperature and power supply variable delay determined by the time required to set up the bit lines; sensing a second row address strobe signal transition to indicate that the chip has entered a precharge period; generating a final sensing signal in response to said second address row signal transition; and terminating said preliminary and final sensing signals at a second predetermined delay after said second row address strobe signal transition.
Claim 20
Independent Claim
134 words
A method for compensating for temperature and power supply variations in a dynamic random access memory circuit to control current surges in said memory circuit, said method comprising: sensing a first row address strobe signal transition to indicate that the chip has entered an active period; generating a preliminary sensing signal in response to said first row address strobe signal transition after a first temperature and power supply variable delay determined by the time required to set up the bit lines; sensing a second row address strobe signal transition to indicate that the chip has entered a precharge period; generating a final sensing signal in response to said second address row signal transition; and terminating said preliminary and final sensing signals at a second predetermined delay after said second row address strobe signal transition.
Claim 21
Independent Claim
65 words
A method for stabilizing current surges during sense and restore operations of a dynamic random access memory circuit having active and precharge periods, said method comprising: generating a first sensing signal in response to initiation of the chip active period; generating a second sensing signal whose timing is not determined by the first sensing signal; and operating circuitry with said first and second sensing signals.
Claim 22
Independent Claim
65 words
A method for stabilizing current surges during sense and restore operations of a dynamic random access memory circuit having active and precharge periods, said method comprising: generating a first sensing signal in response to initiation of the chip active period; generating a second sensing signal whose timing is not determined by the first sensing signal; and operating circuitry with said first and second sensing signals.
References Cited (Backward Citations)
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