Static random access memory with address transition detector

Claim 2

A static random access memory having a memory cell array (MA) containing a plurality of static memory cells (7) for storing data arrayed in a matrix fashion, word lines (4) for selecting rows of the memory cells (7) in said memory cell array (MA), said word lines (4) being arranged along with the rows of said memory cell array (MA), bit line pairs (5, 5 arranged the columns of the memory cells (7) in said memory cell array (MA), said bit line pairs (5, 5 ) each selecting one column of said memory cells to transfer data to and from one of the memory cells of the selected column, address input means (1 and 2) for receiving an address signal (Add) to select one of said memory cells (7) of said memory cell array (MA), row decoder means (3) for decoding a row address signal supplied from said address input means (1 and 2) and to selectively drive said word lines (4), column decoder means (8 and 9) for decoding a column address signal supplied from said address input means (1 and 2) to select one of said bit line pairs (5, 5 ), address transition detector means (13) for detecting a transition of an address signal (Add) supplied from said address input means (1 and 2), to generate an address transition detect signal (SATD), bit line initialize means (6) for initializing a potential of each said bit line pair (5, 5 ) to a predetermined potential, said bit line initialize means (6) being under control of an address transition detect signal outputted from said address transition detector means (13), when a transi­tion of said address signal (Add) is detected, clock signal generator means (14) for generating during a pre­determined period of time elapsing from generation of said address transition detect signal (SATD) in a read mode, said clock signal generator means (14) being coupled for reception an address transition detect sig­nal (SATD) from said address transition detector means (13), and sense amplifier means (10) for amplifying the data as is read out from one selected memory cell (7) to said bit line pair (5, 5 ) associated with said selected memory cell (7), and data output means (11 and 12) for outputting a signal (Dout) corresponding to the data as is read out from said memory cell (7) and outputted from said sense amplifier means (10), characterized in that said sense amplifier means (10) is initialized by an address transition detect signal (SATD) generated by said address transition detector means (13) and is neutralized during a period of time that said sense amplifier means receives a clock signal (φS) from said clock signal generator means (14), and said data output means (11 and 12) is placed in a high impedance state when said sense amplifier means (10) is initialized, outputs the amplified signal from said sense amplifier means (10) during a period that said clock signal (φS) is being generated, and holds the amplified signal dur­ing a period that the generation of said clock signal (φS) stops.

Claim 3

The static random access memory according to claim 1, characterized in that said sense amplifier means (10) includes a differential amplifier means (N6-1, N5-1, N9-1, P6-1, P5-1, N6-2, N5-2, N9-2, P6-2, P5-2) for differentially amplifying the potentials of said paired bit lines (5, 5 ), a pull-up means (N10-1, N10-2, N12) for pulling up output nodes (26, 26 ) of said differential amplifier means (N6-1, N5-1, N9-1, P6-1, P5-1, N6-2, N5-2, N9-2, P6-2, P5-2) in accordance with an address transition detector means (13), and a con­trol means (N8-1, N7-1, P8-1, P7-1, N8-2, N7-2, P8-2, P7-2) for activating said differential amplifier means (N6-1, N5-1, N9-1, P6-1, P5-1, N6-2, N5-2, N9-2, P6-2, P5-2) when a clock signal (φS) is received from said clock signal generator means (14), and for deactivating said differential amplifier means (N6-1, N5-1, N9-1, P6-1, P5-1, N6-2, N5-2, N9-2, P6-2, P5-2) when said clock signal (φS) terminates.

Claim 4

The static random access memory according to claim 1, characterized in that said sense amplifier means (10) includes a first MOSFET (N6-1) of a first conductivity type coupled at the gate with one of said selected paired bit lines (5, 5 ), a second MOSFET (N5-1) of the first conductivity type coupled at the gate with the other of said selected paired bit lines (5, 5 ), an AND gate (34) receiving at one input terminal a clock signal (φS) from said clock signal generator means (14) and at the other input terminal the inverted signal of an address transition detect signal (SATD) from said address transition detector means (13), a third MOSFET (P8-1) of a second conductivity type whose current path is connected between one end of a current path of said first MOSFET (N6-1) and a first potential source (V DD ), and whose conduction is controlled by an output signal of said AND gate (34), a 4th MOSFET (P7-1) of the second conductivity type whose current path is connected be­tween one end of a current path of said second MOSFET (N5-1) and said a first potential source (V DD ), and whose conduction is controlled by an output signal of said AND gate (34), a 5th MOSFET (P6-1) of the second conductivity type whose current path is connected in parallel with the current path of said third MOSFET (P8-1), a 6th MOSFET (P5-1) of the second conductivity type whose current path is connected in parallel with the current path of said 4th MOSFET (P7-1), and whose gate is connected to the gate of said 5th MOSFET (P6-1) and one end of said current path of said first MOSFET (N6-1), a 7th MOSFET (P10-1) of the first conductivity type whose current path is connected between one end of the current path of said first MOSFET (N6-1) and one end of the current path of said second MOSFET (N5-1), and whose gate is coupled for reception with the address transition detect signal (SATD), an 8th MOSFET (N8-1) of the first conductivity type whose current path is connected at one end to the other end of the current path of said first MOSFET (N6-1), and whose gate is coupled for reception with the an output signal of said AND gate (34), a 9th MOSFET (N7-1) of the first conduc­tivity type whose current path is connected at one end to the other end of the current path of said second MOSFET (N5-1), and at the other end with the other end of said 8th MOSFET (N8-1), and whose gate is coupled for reception with an output signal of said AND gate (34), a 10th MOSFET (N9-1) of the first conductivity type whose current path is connected at one end to the other ends of the current paths of said 8th and 9th MOSFETs (N8-1, N7-1), and at the other end with a second potential source, and whose gate is coupled with said first poten­tial source (V DD ), a 11th MOSFET (N5-2) of the first conductivity type whose gate is coupled with the gate of said first MOSFET (N6-1), a 12th MOSFET (N6-2) of the first conductivity type whose gate is coupled with the gate of said second MOSFET (N5-1), a 13th MOSFET (P7-2) of the second conductivity type whose current path is connected between one end of a current path of said 11th MOSFET (N5-2) and said first potential source (V DD ), and whose conduction is controlled by an output signal of said AND gate (34), a 14th MOSFET (P8-2) of the second conductivity type whose current path is connected between one end of a current path of said 12th MOSFET (N6-2) and said first potential source (V DD ), and whose conduction is controlled by an output signal of said AND gate (34), a 15th MOSFET (P5-2) of the second conduc­tivity type whose current path is connected in parallel with the current path of said 13 MOSFET (P7-2), a 16th MOSFET (P5-2) of the second conductivity type whose cur­rent path is connected in parallel with the current path of said 14th MOSFET (P8-2) and whose gate is coupled with the gate of said 15th MOSFET (P5-2) and one end of the current path of said 11th MOSFET (N5-2), a 17th MOSFET (N10-2) of the first conductivity type whose current path is connected between one end of the current path of said 11th MOSFET (N5-2) and one end of the cur­rent path of said 12th MOSFET (N6-2), and whose gate is coupled for reception with the address transition detect signal (SATD), an 18th MOSFET (N7-2) of the first conductivity type whose current path is connected at one end to the other end of the current path of said 11th MOSFET (N5-2), and whose gate is coupled for reception with the an output signal of said AND gate (34), a 19th MOSFET (N8-2) of the first conductivity type whose cur­rent path is connected at one end to the other end of the current path of said 12th MOSFET (N6-2) and at the other end to the other end of the current path of said 18th MOSFET (N7-2), and whose gate is coupled for recep­tion with the an output signal of said AND gate is coupled for recep­tion with the an output signal of said AND gate (34), a 20th MOSFET (N9-1) of the first conductivity type whose current path is connected at one end to the other ends of the current paths of said 18th and 19th MOSFETs (N7-2, N8-2), and at the other end with said second potential source, and whose gate is coupled with said first potential source (V DD ), a 21th MOSFET (N11) of the first conductivity type whose current path is connected between one end of the current path of said second MOSFET (N5-1) and one end of the current path of said 11th MOSFET (N5-2), and whose conduction is controlled by address transition detect signal (SATD), a first sense amplifier output line (26) coupled with one end of the current path of said second MOSFET (N5-1), and a second sense amplifier output line ( 26 ) coupled with one end of the current path of said 11th MOSFET (N5-2).

Claim 5

The static random access memory according to claim 1, characterized in that said data output means (11) includes a master slave flip-flop being reset when the output terminal of said sense amplifier means (10) is pulled up in synchronism with said address transition detect signal (SATD), outputting allowing said sense amplifier means (10) to pass an output signal therethrough when said clock signal (φS) is being generated; an being placed in a data hold state at the termination of said clock signal (φS), a pull-up means (P9) being turned on and off in accordance with the out­put signal of said flip-flop and for pulling up the output terminal, and a pull-down means (N12) being turned on and off in accordance with the output signal of said flip-flop and for pulling down the output terminal.

Claim 6

The static random access memory according to claim 1, characterized in that said data output means (11) includes a first NOR gate (35) having two input terminals, one of said input terminals being connected to the first output line ( 26 ) of said sense amplifier means (10), a second NOR gate (36) having two input terminals, one of said input terminals being connected to the second output line (26) of said sense amplifier means (10), and the other input terminal being connected to the output terminal of said first NOR gate (35), and an output terminal of said second NOR gate being the other input terminal of said first NOR gate (35), a third NOR gate (37) having two input terminals, one of said input terminals being connected to the output ter­minal of said first NOR gate (35), a 4th NOR gate (38) having two input terminals, one of said input terminals being connected to the output terminal of said second NOR gate (36), a first inverter (39) connected at the input terminal to the output line (23) of said clock signal generator means (14), at the output terminal to the other input terminals of said third and 4th NOR gates (37, 38), a 5th NOR gate (40) connected at one of the in-put terminals to the output terminal of said third NOR gate (37), a 6th NOR gate (41) coupled at one of the input terminals with the output terminal of said 4th NOR gate (38), at the other input terminal with the output terminal of said 5th NOR gate (40), and at the output terminal with the other input terminal of said 5th NOR gate (40), a second inverter (42) coupled at the input terminal with the output terminal of said 5th NOR gate (40), a first MOSFET (P9) of a first conductivity type whose current path is connected at one end to a first potential source (V DD ) and at the gate to the output terminal of said second inverter (42), a second MOSFET (N12) of a second conductivity type whose current path is connected between the other end of the current path of said first MOSFET (P9) and a second potential source and at the gate to the output terminal of said 6th NOR gate (41), and a data output terminal (12) coupled a connection point between said first MOSFET (P9) and second MOSFET (N12).

Claim 7

The static random access memory according to claim 1, characterized in that said data output means (11) includes a first NOR gate (43) having two input terminals, one of said input terminals being connected to the first output line ( 26 ) of said sense amplifier means (10) and the other being connected to the output line (23) of said clock signal generator means (14), a second NAND gate (44) having two input terminals, one of said input terminals being connected to the second out­put line (26) of said sense amplifier means (10), and the other input terminal being connected to the output line (23) of said clock signal generator means (14), a third NAND (45) having two input terminals, one of said input terminals being connected to the output terminal of said first NAND gate (43), a 4th NAND gate (46) hav­ing two input terminals, one of said input terminals being connected to the output terminal of said second NAND gate (44) and at the other input terminal with the output terminal of said third NAND gate (45), and the output terminal of said 4th NAND gate being connected to the other input terminal of said third NAND gate (45), an inverter (47) connected at the input terminal to the output terminal of said 4th NAND gate (46), a first MOSFET (P9) of a first conductivity type whose current path is connected at one end to a first potential source (V DD ) and at the gate to the output terminal of said third NAND gate (45), a second MOSFET (N12) of a second conductivity type whose current path is connected between the other end of the current path of said first MOSFET (P9) and a second potential source and at the gate to the output terminal of said inverter (47), and a data output terminal (12) coupled a connection point between said first MOSFET (P9) and second MOSFET (N12).

Claim 8

The static random access memory according to claim 1, characterized by further comprising a data out­put detector means (15) for detecting whether the out­put terminal of said data output means (11) is in a high impedance state or a data outputting state, and a logic means (16) for logically summing the output signal (φS) of said clock signal generator means (14) and the out­put signal of said data output detector means (15) and controlling said sense amplifier means (10) and said data output means (11) on the obtained logical sum.

Claim 9

The static random access memory according to claim 7, characterized in that the period of generating a clock signal (φS) by said clock signal generator means (14) ranges from an instant that said address transition detector means (2) detects a transition of the address signal (Add) till said data output detector means (15) detects the outputting of data.

Claim 10

The static random access memory according to claim 7, characterized in that said logic means includes an OR gate (16).

Claim 11

The static random access memory according to claim 7, characterized in that said data output means (11) includes a first NOR gate (35) having two input terminals, one of said input terminals being connected to the first output line ( 26 ) of said sense amplifier means (10), a second NOR gate (36) having two input terminals, one of said input terminals being connected to the second output line (26) of said sense amplifier means (10), and the other input terminal being connected to the output terminal of said first NOR gate (35), and an output terminal of said second NOR gate (36) being the other input terminal of said first NOR gate (35), a third NOR gate (37) having two input terminals, one of said input terminals being connected to the output ter­minal of said first NOR gate (35), a 4th NOR gate (38) having two input terminals, one of said input terminals being connected to the output terminal of said second NOR gate (36), a first inverter (39) connected at the input terminal to the output line (23) of said clock signal generator means (14), at the output terminal to the other input terminals of said third and 4th NOR gates (37, 38), a 5th NOR gate (40) connected at one of the input terminals to the output terminal of said third NOR gate (37), a 6th NOR gate (40) coupled at one of the input terminals with the output terminal of said 4th NOR gate (38), at the other input terminal with the output terminal of said 5th NOR gate (40), and at the output terminal with the other input terminal of said 5th NOR gate (40), a second inverter (42) coupled at the input terminal with the output terminal of said 5th NOR gate (40), a first MOSFET (P9) of a first conductivity type whose current path is connected at one end to a first potential source (V DD ) and at the gate to the output terminal of said second inverter (42), a second MOSFET (N12)of a second conductivity type whose current path is connected between the other end of the current path of said first MOSFET (P9) and a second potential source and at the gate to the output terminal of said 6th NOR gate (41), and a data output terminal (12) coupled a connection point between said first MOSFET (P9) and second MOSFET (N12), and said data output detecting means includes a 7th NOR gate (48) which is coupled at one of the input terminals with the output terminal of said 5th NOR gate (40), at the other with the output terminal of said 6th NOR gate (41), and at the output terminal with one of the input terminals of said logic means (16).

Claim 12

The static random access memory according to claim 7, characterized in that said data output means (11) includes a first NOR gate (43) having two input terminals, one of said input terminals being connected to the first output line ( 26 ) of said sense amplifier means (10) and the other being connected to the output line (23) of said clock signal generator means (14), a second NAND gate (44) having two input terminals, one of said input terminals being connected to the second out­put line (26) of said sense amplifier means (10), and the other input terminal being connected to the output line (23) of said clock signal generator means (14), a third NAND (45) having two input terminals, one of said input terminals being connected to the output terminal of said first NAND gate (43), a 4th NAND gate (46) hav­ing two input terminals, one of said input terminals being connected to the output terminal of said second NAND gate (44) and at the other input terminal with the output terminal of said third NAND gate (45), and the output terminal of said 4th NAND gate (46) being con­nected to the other input terminal of said third NAND gate (45), an inverter (47) connected at the input ter­minal to the output terminal of said 4th NAND gate (46), a first MOSFET (P9) of a first conductivity type whose current path is connected at one end to a first poten­tial source (V DD ) and at the gate to the output terminal of said third NAND gate (45), a second MOSFET (N12) of a second conductivity type whose current path is connected between the other end of the current path of said first MOSFET (P9) and a second potential source and at the gate to the output terminal of said inverter (47), and a data output terminal (12) coupled a connection point between said first MOSFET (P9) and second MOSFET (N12), and said data output detecting means (15) includes an AND gate (49) which is coupled at one of the input terminals with the output terminal of said third NAND gate (45), at the other with the output terminal of said 4th NAND gate (46), and at the output terminal with one of the input terminals of said logic means (16).