US5920710A
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US
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Apparatus and method for modifying status bits in a reorder buffer with a large speculative state
Assignee: Advanced Micro Devices Inc
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Filing: 1996-11-18
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Granted: 1999-07-06
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Expires: 2016-11-18
Abstract
Abstract A superscalar microprocessor implements a reorder buffer to support out-of-order execution of instructions. To reduce the time delay for identifying mispredicted instructions, prioritizing mispredicted instructions, canceling instructions subsequent to the mispredicted instruction and reading status information from the reorder buffer, the availability of an instruction tag, which identifies the instruction being executed, during the execution of the instruction is utilized. The reorder buffer receives the tag of the instruction issued to the functional unit. In parallel with the execution of the instruction, the reorder buffer generates hit masks identifying instructions to be canceled in the event of a mispredicted branch. In parallel, status information from the instruction (or instructions) being executed is selected from the reorder buffer and prioritization masks are generated. Therefore, if a mispredicted branch is detected, the instructions that need to be canceled can be readily identified and the instruction status information is readily available.
Inventors
- 👤 Teik-Chung Tan
- 👤 Thang M. Tran
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 21:41
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3836; G06F9/3842; G06F9/3861
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
137 words
A reorder buffer for storing results of speculatively executed instructions, comprising: an instruction storage device including a plurality of instruction storage positions configured to store speculatively executed results of instructions; an instruction tag line configured to convey an execution tag signal that identifies a corresponding instruction dispatched to an execution unit, wherein said execution tag signal is configured to be conveyed prior to said corresponding instruction being executed; and a mask generation circuit coupled to said instruction tag line, wherein said mask generation circuit is configured to receive said execution tag signal, wherein said mask generator circuit, prior to or in parallel with said instruction being executed, is configured to generate a mask that indicates which of said speculatively executed results of instructions within said instruction storage device are subsequent in program order to said corresponding instruction.
Claim 2
Dependent Claim
137 words
A reorder buffer for storing results of speculatively executed instructions, comprising: an instruction storage device including a plurality of instruction storage positions configured to store speculatively executed results of instructions; an instruction tag line configured to convey an execution tag signal that identifies a corresponding instruction dispatched to an execution unit, wherein said execution tag signal is configured to be conveyed prior to said corresponding instruction being executed; and a mask generation circuit coupled to said instruction tag line, wherein said mask generation circuit is configured to receive said execution tag signal, wherein said mask generator circuit, prior to or in parallel with said instruction being executed, is configured to generate a mask that indicates which of said speculatively executed results of instructions within said instruction storage device are subsequent in program order to said corresponding instruction.
Claim 3
Dependent Claim
31 words
The reorder buffer of claim 1, further comprising a result status line configured to convey a result status signal that indicates whether said corresponding instruction results is an exception upon execution.
Claim 4
Dependent Claim
30 words
The reorder buffer of claim 2, wherein if said result status signal indicates a branch misprediction has occurred, all speculatively executed results of instructions identified by said mask are canceled.
Claim 5
Dependent Claim
50 words
The reorder buffer of claim 1, further comprising a comparator coupled to said instruction storage device, to said instruction tag line and to said mask generation circuit, wherein said comparator identifies an instruction storage position within said instruction storage device that stores said speculatively executed result of said corresponding instruction.
Claim 6
Dependent Claim
57 words
The reorder buffer of claim 4, wherein said instruction storage positions of said instruction storage device are further configured to store status information of instructions and said reorder buffer further comprises a multiplexer coupled to said instruction storage device and to an output of said comparator, wherein said multiplexer selects status information corresponding to said corresponding instructions.
Claim 7
Dependent Claim
20 words
The reorder buffer of claim 5, wherein said selection by said multiplexer is prior to said corresponding instruction being executed.
Claim 8
Dependent Claim
22 words
The reorder buffer of claim 1, wherein said mask includes a bit for each instruction storage position in said instruction storage device.
Claim 9
Dependent Claim
51 words
The reorder buffer of claim 7, wherein a bit of said mask is deactivated if an instruction corresponding to said bit is earlier in program order than said corresponding instruction, and said bit is activated if said instruction corresponding to said bit is later in program order than said corresponding instruction.
Claim 10
Independent Claim
124 words
A method for restoring a program state of a reorder buffer comprising the steps of: receiving an execution tag signal in a mask generation circuit from an instruction tag line, wherein said execution tag signal identifies a corresponding instruction dispatched for execution prior to said corresponding instruction being executed; generating a plurality of masks in said mask generation circuit, wherein said masks identify which of a plurality of speculatively executed results of instructions within said reorder buffer are subsequent in program order to said corresponding instruction and said masks are generated prior to or in parallel with said corresponding instruction being executed; and receiving a result status signal, wherein said result status signal indicates whether said corresponding instruction results is an exception upon execution.
Claim 11
Independent Claim
124 words
A method for restoring a program state of a reorder buffer comprising the steps of: receiving an execution tag signal in a mask generation circuit from an instruction tag line, wherein said execution tag signal identifies a corresponding instruction dispatched for execution prior to said corresponding instruction being executed; generating a plurality of masks in said mask generation circuit, wherein said masks identify which of a plurality of speculatively executed results of instructions within said reorder buffer are subsequent in program order to said corresponding instruction and said masks are generated prior to or in parallel with said corresponding instruction being executed; and receiving a result status signal, wherein said result status signal indicates whether said corresponding instruction results is an exception upon execution.
Claim 12
Dependent Claim
34 words
The method for restoring a program state of a reorder buffer of claim 9 further comprising the step of selecting status information corresponding to said corresponding instruction prior to said corresponding instruction being executed.
Claim 13
Dependent Claim
34 words
The method for restoring a program state of a reorder buffer of claim 9 further comprising the step of comparing said execution tag signal to tags of instruction results stored in said reorder buffer.
Claim 14
Dependent Claim
38 words
The method for restoring a program state of a reorder buffer of claim 9 further comprising the step of canceling instructions identified by said mask if said result status signal indicates said corresponding instruction results in an exception.
Claim 15
Dependent Claim
174 words
A microprocessor comprising: an instruction cache; a decode unit coupled to said instruction cache; a functional unit coupled to said decode unit; a reorder buffer coupled to said functional unit and said decode unit, wherein said reorder buffer includes: an instruction storage device including a plurality of instruction storage positions configured to store speculatively executed results of instructions, an instruction tag line configured to convey an execution tag signal that identifies a corresponding instruction dispatched to an execution unit, wherein said execution tag signal is configured to be conveyed prior to said corresponding instruction being executed; and a mask generation circuit coupled to said instruction tag line, wherein said mask generation circuit is configured to receive said execution tag signal, wherein said mask generator circuit, prior to or in parallel with said instruction being executed, is configured to generate a mask that indicates which of said speculatively executed results of instructions within said instruction storage device are subsequent in program order to said corresponding instruction; and a register file coupled to said reorder buffer.
Claim 16
Dependent Claim
174 words
A microprocessor comprising: an instruction cache; a decode unit coupled to said instruction cache; a functional unit coupled to said decode unit; a reorder buffer coupled to said functional unit and said decode unit, wherein said reorder buffer includes: an instruction storage device including a plurality of instruction storage positions configured to store speculatively executed results of instructions, an instruction tag line configured to convey an execution tag signal that identifies a corresponding instruction dispatched to an execution unit, wherein said execution tag signal is configured to be conveyed prior to said corresponding instruction being executed; and a mask generation circuit coupled to said instruction tag line, wherein said mask generation circuit is configured to receive said execution tag signal, wherein said mask generator circuit, prior to or in parallel with said instruction being executed, is configured to generate a mask that indicates which of said speculatively executed results of instructions within said instruction storage device are subsequent in program order to said corresponding instruction; and a register file coupled to said reorder buffer.
Claim 17
Dependent Claim
30 words
The microprocessor of claim 13, further comprising a result status line configured to convey a result status signal that indicates whether said corresponding instruction results is an exception upon execution.
Claim 18
Dependent Claim
29 words
The microprocessor of claim 14, wherein if said result status signal indicates a branch misprediction has occurred, all speculatively executed results of instructions identified by said mask are canceled.
Claim 19
Dependent Claim
49 words
The microprocessor of claim 13, further comprising a comparator coupled to said instruction storage device, to said instruction tag line and to said mask generation circuit, wherein said comparator identifies an instruction storage position within said instruction storage device that stores said speculatively executed result of said corresponding instruction.
Claim 20
Dependent Claim
56 words
The microprocessor of claim 16, wherein said instruction storage positions of said instruction storage device are further configured to store status information of instructions and said reorder buffer further comprises a multiplexer coupled to said instruction storage device and to an output of said comparator, wherein said multiplexer selects status information corresponding to said corresponding instructions.
Claim 21
Dependent Claim
19 words
The microprocessor of claim 17, wherein said selection by said multiplexer is prior to said corresponding instruction being executed.
Claim 22
Dependent Claim
21 words
The microprocessor of claim 13, wherein said mask includes a bit for each instruction storage position in said instruction storage device.
Claim 23
Dependent Claim
50 words
The microprocessor of claim 19, wherein a bit of said mask is deactivated if an instruction corresponding to said bit is earlier in program order than said corresponding instruction, and said bit is activated if said instruction corresponding to said bit is later in program order than said corresponding instruction.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-07-05 | 2003-01-04 | 2003-07-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-07-05 | 2007-01-04 | 2007-07-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-07-05 | 2011-01-04 | 2011-07-06 | $7700.00 | Window Closed / Lapsed |