Coordinating speculative and committed state register source data and immediate source data in a processor

Claim 3

The method of claim 1, wherein the instruction further comprises at least one immediate valid flag, the immediate valid flag indicating whether the instruction includes an immediate operand.

Claim 4

The method of claim 2, further comprising the step of storing the immediate operand into the dispatch buffer and storing an immediate operand valid flag indicating that the immediate operand is valid into the valid flag of the dispatch buffer if the immediate valid flag specifies the immediate operand.

Claim 5

The method of claim 1, wherein the physical register source comprises a register pointer and a real register valid flag, the real register valid flag indicating whether the register pointer specifies the physical register or the committed state register.

Claim 6

The method of claim 1, wherein the speculative source valid flag indicates whether the speculative source data value is a speculative result data value has been produced by completed execution of another instruction.

Claim 7

The method of claim 1, wherein each instruction comprises a source one immediate valid flag, a source two immediate valid flag, a first logical register source, and a second logical register source, the source one and source two immediate valid flags indicating whether the instruction includes an immediate operand.

Claim 8

The method of claim 6, wherein the step of generating a physical register source by renaming the logical register source comprises the steps of generating a first physical register source by renaming the first logical register source and generating a second physical register source by renaming the second logical register source, such that the first and second physical register sources each specify a physical register or a committed state register.

Claim 9

The method of claim 7, wherein the step of reading a speculative result data value and a speculative source valid flag from the physical register comprises the steps of reading a first speculative result data value and a first speculative source valid flag from the first physical register if the first physical register source specifies the first physical register, and reading a second speculative result data value and a second speculative source valid flag from the second physical register if the second physical register source specifies the second physical register.

Claim 10

The method of claim 8, wherein the step of reading a committed result data value from the committed state register comprises the steps of reading a first committed result data value from the first committed state register if the first physical register source specifies the first committed state register, and reading a second committed result data value from the second committed state register if the second physical register source specifies the second committed state register.

Claim 11

The method of claim 9, wherein the steps of storing the speculative result data value into a dispatch buffer and storing the speculative source valid flag into a valid flag in the dispatch buffer and storing the committed result data value into the dispatch buffer and storing a committed source valid flag indicating that the committed result data value is valid into the valid flag of the dispatch buffer comprises the steps of: storing the immediate operand into the dispatch buffer and storing the source one immediate valid flag into the valid flag in the dispatch buffer if the source one immediate valid flag indicates that the immediate operand replaces the first speculative result data value; storing the first speculative result data value into the dispatch buffer and storing the first speculative source valid flag into the valid flag in the dispatch buffer if the first physical register source specifies the first physical register and if the source one immediate valid flag does not indicate that the immediate operand replaces the first speculative result data value.

Claim 12

The method of claim 9, wherein the steps of storing the speculative result data value into a dispatch buffer and storing the speculative source valid flag into a valid flag in the dispatch buffer and storing the committed result data value into the dispatch buffer and storing a committed source valid flag indicating that the committed result data value is valid into the valid flag of the dispatch buffer comprises the steps of: storing the immediate operand into the dispatch buffer and storing the source two immediate valid flag into the valid flag in the dispatch buffer if the source two immediate valid flag indicates that the immediate operand replaces the second speculative result data value; storing the second speculative result data value into the dispatch buffer and storing the second speculative source valid flag into the valid flag in the dispatch buffer if the second physical register source specifies the second physical register and if the source two immediate valid flag does not indicate that the immediate operand replaces the second speculative result data value.

Claim 15

The apparatus of claim 12, wherein the instruction further comprises at least one immediate valid flag, the immediate valid flag indicating whether the instruction includes an immediate operand.

Claim 16

The apparatus of claim 13, further comprising means for storing the immediate operand into the dispatch buffer and storing an immediate operand valid flag indicating that the immediate operand is valid into the valid flag of the dispatch buffer if the immediate valid flag specifies the immediate operand.

Claim 17

The apparatus of claim 12, wherein the physical register source comprises a register pointer and a real register valid flag, the real register valid flag indicating whether the register pointer specifies the physical register or the committed state register.

Claim 18

The apparatus of claim 12, wherein the speculative source valid flag indicates whether the speculative source data value is a speculative result data value has been produced by completed execution of another instruction.

Claim 19

The apparatus of claim 12, wherein each instruction comprises a source one immediate valid flag, a source two immediate valid flag, a first logical register source, and a second logical register source, the source one and source two immediate valid flags indicating whether the instruction includes an immediate operand.

Claim 20

The apparatus of claim 12, wherein the means for generating a physical register source by renaming the logical register source comprises means for generating a first physical register source by renaming the first logical register source and generating a second physical register source by renaming the second logical register source, such that the first and second physical register sources each specify a physical register or a committed state register.

Claim 21

The apparatus of claim 18, wherein the means for reading a speculative result data value and a speculative source valid flag from the physical register comprises means for reading a first speculative result data value and a first speculative source valid flag from the first physical register if the first physical register source specifies the first physical register, and reading a second speculative result data value and a second speculative source valid flag from the second physical register if the second physical register source specifies the second physical register.

Claim 22

The apparatus of claim 19, wherein the means for reading a committed result data value from the committed state register comprises means for reading a first committed result data value from the first committed state register if the first physical register source specifies the first committed state register, and reading a second committed result data value from the second committed state register if the second physical register source specifies the second committed state register.

Claim 23

The apparatus of claim 20, wherein the means for storing the speculative result data value into a dispatch buffer and storing the speculative source valid flag into a valid flag in the dispatch buffer and storing the committed result data value into the dispatch buffer and storing a committed source valid flag indicating that the committed result data value is valid into the valid flag of the dispatch buffer comprises: means for storing the immediate operand into the dispatch buffer and storing the source one immediate valid flag into the valid flag in the dispatch buffer if the source one immediate valid flag indicates that the immediate operand replaces the first speculative result data value; means for storing the first speculative result data value into the dispatch buffer and storing the first speculative source valid flag into the valid flag in the dispatch buffer if the first physical register source specifies the first physical register and if the source one immediate valid flag does not indicate that the immediate operand replaces the first speculative result data value.

Claim 24

The apparatus of claim 21, wherein the means for storing the speculative result data value into a dispatch buffer and storing the speculative source valid flag into a valid flag in the dispatch buffer and storing the committed result data value into the dispatch buffer and storing a committed source valid flag indicating that the committed result data value is valid into the valid flag of the dispatch buffer comprises: means for storing the immediate operand into the dispatch buffer and storing the source two immediate valid flag into the valid flag in the dispatch buffer if the source two immediate valid flag indicates that the immediate operand replaces the second speculative result data value; means for storing the second speculative result data value into the dispatch buffer and storing the second speculative source valid flag into the valid flag in the dispatch buffer if the second physical register source specifies the second physical register and if the source two immediate valid flag does not indicate that the immediate operand replaces the second speculative result data value.

Claim 25

A processor, comprising: register rename circuit receiving an instruction comprising at least one logical register source, the register rename circuit generating a physical register source by renaming the logical register source, such that the physical register source specifies a physical register or a committed state register; reorder buffer containing the physical register, the reorder buffer receiving the physical register source from the register rename circuit and reading a speculative result data value and a speculative source valid flag from the physical register and transferring and transferring the speculative result data value and the speculative source valid flag over a speculative source data bus if the physical register source specifies the physical register, the speculative source valid flag indicating whether the speculative source data value is valid; real register file containing the committed state register, receiving the physical register source from the register rename circuit and reading a committed result data value from the committed state register and transferring the committed result data value over a committed source data bus if physical register source specifies the committed state register; first multiplexer coupled to the speculative source data bus and the committed source data bus, the first multiplexer transferring the speculative result data value the speculative source valid flag over a source data bus as a source data value and a valid flag if the physical register source specifies the physical register, the first multiplexer transferring the committed result data value and a committed source valid flag indicating that the committed result data value is valid over the source data bus as the source data value and the valid flag if the physical register source specifies the committed state register; dispatch circuit receiving the source data value and the valid flag over the source data bus, the dispatch circuit storing the source data value and the valid flag and scheduling execution of the instruction according to the valid flag.

Claim 26

A processor, comprising: register rename circuit receiving an instruction comprising at least one logical register source, the register rename circuit generating a physical register source by renaming the logical register source, such that the physical register source specifies a physical register or a committed state register; reorder buffer containing the physical register, the reorder buffer receiving the physical register source from the register rename circuit and reading a speculative result data value and a speculative source valid flag from the physical register and transferring and transferring the speculative result data value and the speculative source valid flag over a speculative source data bus if the physical register source specifies the physical register, the speculative source valid flag indicating whether the speculative source data value is valid; real register file containing the committed state register, receiving the physical register source from the register rename circuit and reading a committed result data value from the committed state register and transferring the committed result data value over a committed source data bus if physical register source specifies the committed state register; first multiplexer coupled to the speculative source data bus and the committed source data bus, the first multiplexer transferring the speculative result data value the speculative source valid flag over a source data bus as a source data value and a valid flag if the physical register source specifies the physical register, the first multiplexer transferring the committed result data value and a committed source valid flag indicating that the committed result data value is valid over the source data bus as the source data value and the valid flag if the physical register source specifies the committed state register; dispatch circuit receiving the source data value and the valid flag over the source data bus, the dispatch circuit storing the source data value and the valid flag and scheduling execution of the instruction according to the valid flag.

Claim 27

The processor of claim 23, wherein the instruction further comprises at least one immediate valid flag, the immediate valid flag indicating whether the instruction includes an immediate operand.

Claim 28

The processor of claim 24, further comprising a second multiplexer coupled to receive the source data value and the valid flag over the source data bus and coupled to receive the immediate operand, the second multiplexer transferring the immediate operand and an immediate operand valid flag indicating that the immediate operand is valid over the source data bus as the source data value and the valid flag if the immediate valid flag specifies the immediate operand.

Claim 29

The processor of claim 23, wherein the physical register source comprises a register pointer and a real register valid flag, the real register valid flag indicating whether the register pointer specifies the physical register or the committed state register.

Claim 30

The processor of claim 23, wherein the speculative source valid flag indicates whether the speculative source data value is a speculative result data value has been produced by completed execution of another instruction.

Claim 31

A computer system, comprising: memory subsystem coupled for communication over a host bus, the memory subsystem storing an instruction; means for fetching the instruction over the host bus, the instruction comprising at least one logical register source; means for generating a physical register source by renaming the logical register source, such that the physical register source specifies a physical register or a committed state register; means for reading a speculative result data value and a speculative source valid flag from the physical register if the physical register source specifies the physical register, the speculative source valid flag indicating whether the speculative source data value is valid; means for reading a committed result data value from the committed state register if physical register source specifies the committed state register; means for storing the speculative result data value into a dispatch buffer and storing the speculative source valid flag into a valid flag in the dispatch buffer if the physical register source specifies the physical register; means for storing the committed result data value into the dispatch buffer and storing a committed source valid flag indicating that the committed result data value is valid into the valid flag of the dispatch buffer if the physical register source specifies the committed state register; means for scheduling execution of the instruction according to the valid flag in the dispatch buffer.

Claim 32

A computer system, comprising: memory subsystem coupled for communication over a host bus, the memory subsystem storing an instruction; means for fetching the instruction over the host bus, the instruction comprising at least one logical register source; means for generating a physical register source by renaming the logical register source, such that the physical register source specifies a physical register or a committed state register; means for reading a speculative result data value and a speculative source valid flag from the physical register if the physical register source specifies the physical register, the speculative source valid flag indicating whether the speculative source data value is valid; means for reading a committed result data value from the committed state register if physical register source specifies the committed state register; means for storing the speculative result data value into a dispatch buffer and storing the speculative source valid flag into a valid flag in the dispatch buffer if the physical register source specifies the physical register; means for storing the committed result data value into the dispatch buffer and storing a committed source valid flag indicating that the committed result data value is valid into the valid flag of the dispatch buffer if the physical register source specifies the committed state register; means for scheduling execution of the instruction according to the valid flag in the dispatch buffer.

Claim 33

The computer system of claim 28, wherein the instruction further comprises at least one immediate valid flag, the immediate valid flag indicating whether the instruction includes an immediate operand.

Claim 34

The computer system of claim 29, further comprising means for storing the immediate operand into the dispatch buffer and storing an immediate operand valid flag indicating that the immediate operand is valid into the valid flag of the dispatch buffer if the immediate valid flag specifies the immediate operand.

Claim 35

The computer system of claim 28, wherein the physical register source comprises a register pointer and a real register valid flag, the real register valid flag indicating whether the register pointer specifies the physical register or the committed state register.

Claim 36

The computer system of claim 28, wherein the speculative source valid flag indicates whether the speculative source data value is a speculative result data value has been produced by completed execution of another instruction.

Claim 37

The computer system of claim 28, wherein each instruction comprises a source one immediate valid flag, a source two immediate valid flag, a first logical register source, and a second logical register source, the source one and source two immediate valid flags indicating whether the instruction includes an immediate operand.

Claim 38

The computer system of claim 28, wherein the means for generating a physical register source by renaming the logical register source comprises means for generating a first physical register source by renaming the first logical register source and generating a second physical register source by renaming the second logical register source, such that the first and second physical register sources each specify a physical register or a committed state register.

Claim 39

The computer system of claim 34, wherein the means for reading a speculative result data value and a speculative source valid flag from the physical register comprises means for reading a first speculative result data value and a first speculative source valid flag from the first physical register if the first physical register source specifies the first physical register, and reading a second speculative result data value and a second speculative source valid flag from the second physical register if the second physical register source specifies the second physical register.

Claim 40

The computer system of claim 35, wherein the means for reading a committed result data value from the committed state register comprises means for reading a first committed result data value from the first committed state register if the first physical register source specifies the first committed state register, and reading a second committed result data value from the second committed state register if the second physical register source specifies the second committed state register.

Claim 41

The computer system of claim 36, wherein the means for storing the speculative result data value into a dispatch buffer and storing the speculative source valid flag into a valid flag in the dispatch buffer and storing the committed result data value into the dispatch buffer and storing a committed source valid flag indicating that the committed result data value is valid into the valid flag of the dispatch buffer comprises: means for storing the immediate operand into the dispatch buffer and storing the source one immediate valid flag into the valid flag in the dispatch buffer if the source one immediate valid flag indicates that the immediate operand replaces the first speculative result data value; means for storing the first speculative result data value into the dispatch buffer and storing the first speculative source valid flag into the valid flag in the dispatch buffer if the first physical register source specifies the first physical register and if the source one immediate valid flag does not indicate that the immediate operand replaces the first speculative result data value.

Claim 42

The computer system of claim 37, wherein the means for storing the speculative result data value into a dispatch buffer and storing the speculative source valid flag into a valid flag in the dispatch buffer and storing the committed result data value into the dispatch buffer and storing a committed source valid flag indicating that the committed result data value is valid into the valid flag of the dispatch buffer comprises: means for storing the immediate operand into the dispatch buffer and storing the source two immediate valid flag into the valid flag in the dispatch buffer if the source two immediate valid flag indicates that the immediate operand replaces the second speculative result data value; means for storing the second speculative result data value into the dispatch buffer and storing the second speculative source valid flag into the valid flag in the dispatch buffer if the second physical register source specifies the second physical register and if the source two immediate valid flag does not indicate that the immediate operand replaces the second speculative result data value.

Claim 43

A computer system, comprising: memory subsystem coupled for communication over a host bus, the memory subsystem storing an instruction comprising at least one logical register source; processor coupled to the host bus, the processor fetching the instruction from the memory subsystem, the processor generating a physical register source by renaming the logical register source, such that the physical register source specifies a physical register or a committed state register, the processor reading a speculative result data value and a speculative source valid flag from the physical register if the physical register source specifies the physical register, the processor reading a committed result data value from the committed state register if physical register source specifies the committed state register, the processor combining the speculative result data value the speculative source valid flag with the committed result data value and a committed source valid flag, the processor scheduling execution of the instruction according to the combined speculative and committed source valid flags.

Claim 44

A computer system, comprising: memory subsystem coupled for communication over a host bus, the memory subsystem storing an instruction comprising at least one logical register source; processor coupled to the host bus, the processor fetching the instruction from the memory subsystem, the processor generating a physical register source by renaming the logical register source, such that the physical register source specifies a physical register or a committed state register, the processor reading a speculative result data value and a speculative source valid flag from the physical register if the physical register source specifies the physical register, the processor reading a committed result data value from the committed state register if physical register source specifies the committed state register, the processor combining the speculative result data value the speculative source valid flag with the committed result data value and a committed source valid flag, the processor scheduling execution of the instruction according to the combined speculative and committed source valid flags.

Claim 45

The computer system of claim 39, wherein the processor comprises: register rename circuit receiving the instruction and generating the physical register source by renaming the logical register source, such that the physical register source specifies a physical register or a committed state register; reorder buffer containing the physical register, the reorder buffer receiving the physical register source from the register rename circuit and reading the speculative result data value and the speculative source valid flag from the physical register and transferring and transferring the speculative result data value and the speculative source valid flag over a speculative source data bus if the physical register source specifies the physical register, the speculative source valid flag indicating whether the speculative source data value is valid; real register file containing the committed state register, receiving the physical register source from the register rename circuit and reading the committed result data value from the committed state register and transferring the committed result data value over a committed source data bus if physical register source specifies the committed state register; first multiplexer coupled to the speculative source data bus and the committed source data bus, the first multiplexer transferring the speculative result data value the speculative source valid flag over a source data bus as a source data value and a valid flag if the physical register source specifies the physical register, the first multiplexer transferring the committed result data value and a committed source valid flag indicating that the committed result data value is valid over the source data bus as the source data value and the valid flag if the physical register source specifies the committed state register; dispatch circuit receiving the source data value and the valid flag over the source data bus, the dispatch circuit storing the source data value and the valid flag and scheduling execution of the instruction according to the valid flag.

Claim 46

The computer system of claim 40, wherein the instruction further comprises at least one immediate valid flag, the immediate valid flag indicating whether the instruction includes an immediate operand.

Claim 47

The computer system of claim 41, wherein the processor further comprises a second multiplexer coupled to receive the source data value and the valid flag over the source data bus and coupled to receive the immediate operand, the second multiplexer transferring the immediate operand and an immediate operand valid flag indicating that the immediate operand is valid over the source data bus as the source data value and the valid flag if the immediate valid flag specifies the immediate operand.

Claim 48

The computer system of claim 40, wherein the physical register source comprises a register pointer and a real register valid flag, the real register valid flag indicating whether the register pointer specifies the physical register or the committed state register.

Claim 49

The computer system of claim 40, wherein the speculative source valid flag indicates whether the speculative source data value is a speculative result data value has been produced by completed execution of another instruction.