EP0381471A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Method and apparatus for preprocessing multiple instructions in a pipeline processor
Assignee: Digital Equipment Corp
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Filing: 1990-01-31
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Granted: —
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Expires: 2010-01-31
Abstract
Abstract To increase the performance of a pipelined processor executing various classes of instructions, the classes of instructions are executed by respective functional units(164-167) which are independently controlled and operated in parallel. The classes of instructions include integer instructions (164) floating point instructions (165), multiply instructions (166), and divide instructions (161). The integer unit, which also performs shift operations, is controlled by the microcode execution unit (26) to handle the wide variety of integer and shift operations included in a complex, variable-length instruction set. The other functional units need only accept a control command to initiate the operation to be performed by the functional unit. The retiring of the results of the instructions need not be controlled by the microcode execution unit, but instead is delegated to a separate retire unit (173) that services a result queue (172). When the microcode execution unit determines that a new operation is required, an entry is inserted into the result queue. The entry includes all the information needed by the retire unit to retire the result once the result is available from the respective functional unit. The retire unit services the result queue by reading a tag in the entry at the head of the queue to determine the functional unit that is to provide the result. Once the result is available and the destination specified by the entry is also available, the result is retired in accordance with the entry, and the entry is removed from the queue.
Inventors
- 👤 William R. Grundmann
- 👤 Ronald M. Salett
- 👤 Francis X. Mckeen
- 👤 Elaine H. Fite
- 👤 Tryggve Fossum
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 08:21
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/30145; G06F9/3016; G06F9/30167; G06F9/30098; G06F9/30101; G06F9/38; G06F9/3836; G06F9/3854; G06F9/3858; G06F9/3861; G06F9/3863; G06F9/3867; G06F9/3885
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
96 words
A method of preprocessing and executing multiple instructions in a pipelined processor, the instructions including opcodes and operand specifiers, the pipelined processor including multiple and separate functional units (164, 165, 166, 167) for executing various classes of instructions, the method comprising: decoding the instructions to obtain the opcodes and operand specifiers; fetching source operands specified by the operand specifiers; issuing the source operands to the respective functional units as indicated by the decoded opcodes, and operating the functional units in parallel to execute the various classes of instructions; and retiring results from the respective functional units.
Claim 2
Independent Claim
96 words
A method of preprocessing and executing multiple instructions in a pipelined processor, the instructions including opcodes and operand specifiers, the pipelined processor including multiple and separate functional units (164, 165, 166, 167) for executing various classes of instructions, the method comprising: decoding the instructions to obtain the opcodes and operand specifiers; fetching source operands specified by the operand specifiers; issuing the source operands to the respective functional units as indicated by the decoded opcodes, and operating the functional units in parallel to execute the various classes of instructions; and retiring results from the respective functional units.
Claim 3
Dependent Claim
31 words
A method as claimed in claim 1, wherein the classes of instructions executed in parallel by the respective functional units include integer instructions, floating point instructions, multiply instructions, and divide instructions.
Claim 4
Dependent Claim
28 words
A method as claimed in claim 1 or 2, wherein the source operands are issued to the respective functional units by a microcode controlled instruction issue unit (25).
Claim 5
Dependent Claim
46 words
A method as claimed in claim 1, 2 or 3 further comprising inserting an entry into a result queue (172) when an instruction is issued to a functional unit, the entry indicating the particular functional unit and the destination for the result of the functional unit.
Claim 6
Dependent Claim
59 words
A method as claimed in claim 4, wherein the entry is inserted into the result queue in response to a signal from a microcode execution unit (26) when the microcode execution unit determines that a new operation is required, the respective functional unit is not busy, the source operands are available, and the destination for the result is known.
Claim 7
Dependent Claim
25 words
A method as claimed in claim 4 or 5, wherein the entry includes a flag indicating whether the result is to be written into memory.
Claim 8
Dependent Claim
21 words
A method as claimed in claim 4, 5 or 6 wherein the entry includes a context field indicating the result context.
Claim 9
Independent Claim
20 words
A method as claimed in any of claims 4 to 7 wherein the entry includes flags for enabling condition codes.
Claim 10
Independent Claim
24 words
A method as claimed in any of claims 4 to 8 wherein the entry includes a flag that marks the end of a microinstruction.
Claim 11
Independent Claim
46 words
A method as claimed in any of claims 4 to 9, further comprising retiring the result from the functional unit indicated by the entry at the head of the result queue when the result is available and when the destination indicated by the entry is available.
Claim 12
Dependent Claim
24 words
A method as claimed in claim 10, further comprising removing the entry from the head of the result queue when the result is retired.
Claim 13
Independent Claim
28 words
A method as claimed in any preceding claim, wherein the results of instructions are retired in the same sequence in which the instructions appear in the instruction stream.
Claim 14
Dependent Claim
99 words
A pipelined processor for preprocessing and executing multiple instructions, the instructions including opcodes and operand specifiers, the processor including means (20) for decoding the instructions to obtain the opcodes and the operand specifiers, means (21) for fetching source operands specified by the operand specifiers, multiple and separate functional units (164, 165, 166, 167) for executing various classes of the instructions, means (25) responsive to the decoded opcodes for issuing commands and source operands to the respective functional units to initiate parallel execution of the various classes of instructions, and means (27) for retiring results from the respective functional units.
Claim 15
Dependent Claim
99 words
A pipelined processor for preprocessing and executing multiple instructions, the instructions including opcodes and operand specifiers, the processor including means (20) for decoding the instructions to obtain the opcodes and the operand specifiers, means (21) for fetching source operands specified by the operand specifiers, multiple and separate functional units (164, 165, 166, 167) for executing various classes of the instructions, means (25) responsive to the decoded opcodes for issuing commands and source operands to the respective functional units to initiate parallel execution of the various classes of instructions, and means (27) for retiring results from the respective functional units.
Claim 16
Dependent Claim
24 words
A pipelined processor as claimed in claim 13, wherein the means for issuing commands and source operands includes a microcode controlled issue unit (25).
Claim 17
Dependent Claim
31 words
A pipelined processor as claimed in claim 14, wherein the functional units include an integer unit (164) controlled by the microcode, the other functional units being controlled independently of the microcode.
Claim 18
Dependent Claim
35 words
A pipelined processor as claimed in claim 13 or 14, wherein the functional units include an integer and shifter unit (164), a floating point unit (165), a multiply unit (166) and a divider unit (167).
Claim 19
Dependent Claim
18 words
A pipelined processor as claimed in claim 16 wherein the integer and shifter unit is controlled by microcode.
Claim 20
Dependent Claim
26 words
A pipelined processor as claimed in claim 17, wherein the floating point unit, the multiply unit and the divider unit are not controlled by the microcode.
Claim 21
Dependent Claim
69 words
A pipelined processor as claimed in any of claims 13 to 18, wherein the means for retiring results from the respective functional units includes a result queue (172), means for loading entries into the result queue, identifying respective functional units and respective destinations for their results, and means (173) for retiring results from respective functional units and to respective destinations as indicated by the entries in the result queue.
References Cited (Backward Citations)
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