EP0259095A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Cache storage queue
Assignee: Fujitsu IT Holdings Inc
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Filing: 1987-08-26
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Granted: —
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Expires: 2007-08-26
Abstract
Abstract In a pipeline data processing machine having a first unit for execution of instructions running according to a first pipeline and a second unit for storing data from a plurality of ports running according to a second pipeline, the first unit having a result register for holding results including data and address information of a flow of the first pipeline, the present invention provides an apparatus for transferring results in the result register to the second unit. A plurality of registers connected to the result register, each storing the result from at least one flow of the first pipeline and storing control information is provided. Further, a controller in communication with the second unit and the plurality of ports responsive to the control information and a flow of the second pipeline is included for selecting one of the plurality of ports in a first-in, first-out queue as a port to the second unit and for updating the control information.
Inventors
- 👤 Kevin L. Daberkow
- 👤 Christopher D. Finan
- 👤 Joseph A. Petolino, Jr.
- 👤 Daniel D. Sobottka
- 👤 Jeffrey A. Thomas
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-28 17:38
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0804; G06F12/0844; G06F12/0855; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3824
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
174 words
In a pipelined data processing machine having a first unit for execution of instructions running according to a first pipeline and a second unit for storing data from a plurality of ports running according to a second pipeline, the first unit having a result register for holding results from a flow of the first pipeline and means for supplying addresses for the results, an apparatus for transferring the results in the result register to the second unit, comprising: a plurality of registers connected to receive results from the result register and to supply the results to the second unit, each of the plurality of registers including means for storing the result from at least one flow of the first pipeline, and means for storing control information for the register; and control means, in communication with the second unit and the plurality of registers, responsive to the control information and a flow of the second pipeline for selecting one of the registers as a port to the second unit and for updating the control information.
Claim 2
Dependent Claim
174 words
In a pipelined data processing machine having a first unit for execution of instructions running according to a first pipeline and a second unit for storing data from a plurality of ports running according to a second pipeline, the first unit having a result register for holding results from a flow of the first pipeline and means for supplying addresses for the results, an apparatus for transferring the results in the result register to the second unit, comprising: a plurality of registers connected to receive results from the result register and to supply the results to the second unit, each of the plurality of registers including means for storing the result from at least one flow of the first pipeline, and means for storing control information for the register; and control means, in communication with the second unit and the plurality of registers, responsive to the control information and a flow of the second pipeline for selecting one of the registers as a port to the second unit and for updating the control information.
Claim 3
Dependent Claim
33 words
The apparatus of claim 1, wherein each of said plurality of registers further include: means in communication with the means for supplying addresses for storing an address of a result in the register.
Claim 4
Dependent Claim
88 words
The apparatus of claim 2, wherein the second unit includes a high speed cache in communication with a main storage system, the high speed cache storing lines of data from the main storage system for quick access by the first unit; the apparatus further including: means, in communication with each of the plurality of registers, for determining whether a result in a given register resides in a line from the main storage system that is present in the high speed cache or missing from the high speed cache.
Claim 5
Dependent Claim
62 words
The apparatus of claim 3, further including means, responsive to the detection of a missing line, for causing the missing line to be moved into the high speed cache from the main storage system; and means, responsive to a move-in of a line, for initiating a transfer of the results from one of the plurality of registers to the high speed cache.
Claim 6
Dependent Claim
111 words
The apparatus of claim 3, wherein the main storage unit includes means for storing a change identifier with each page of data, each page including a plurality of lines of data, in the main storage system indicating changes to the page, the control means further including: means for generating a set change identifier signal in response to the storage of a result from one of the plurality of registers to the high speed cache; means, in communication with the main storage system, for setting the change identifier on a page corresponding to the result from the one register; and means for signaling the control means when the change identifier is set.
Claim 7
Dependent Claim
86 words
The apparatus of claim 3, wherein the plurality of ports includes at least one port from which a request to fetch a line of data from the high speed cache is initiated; the apparatus further including: means for comparing an address of a fetch from the at least one port with addresses stored in the plurality of registers; means responsive to a match for disabling the fetch pending a transfer of results in the plurality of registers having a matching address to the high speed cache.
Claim 8
Dependent Claim
55 words
The apparatus of claim 1, wherein the control means further includes: means for maintaining a first-in, first-out queue for the plurality of registers identifying a sequence in which the plurality of registers receive results from the first unit; and the control means being responsive to the queue for selecting one of the plurality of registers.
Claim 9
Dependent Claim
53 words
The apparatus of claim 1, wherein the results in the result register include up to a number N bits of data, and each of the plurality of registers is capable of storing up to a multiple M times N bits whereby more than one result can be stored in each of the registers.
Claim 10
Dependent Claim
265 words
In a pipeline data processing machine having first unit for execution of instructions running according to a first pipeline and a second unit including a high speed cache and a main store for storing data from a plurality of ports running according to a second pipeline, the high speed cache storing lines of data from the main store for quick access by the first unit, the first unit having a result register for holding results of the flow of the first pipeline and means for supplying addresses for the results, an apparatus for transferring the results in the result register to the high speed cache, comprising: a plurality of registers connected to receive results from the result register and to supply the results to the high speed cache, each of the plurality of registers including means for storing the result from at least one flow of the first pipeline, means for storing address information for the result of the at least one flow of the first pipeline, and means for storing control information for the register; and control means, in communication with the second unit and the plurality of registers, responsive to the control information and a flow of the second pipeline for selecting one of the registers as a port to the second unit and for updating the control information including means for maintaining a first-in, first-out queue for the plurality of registers identifying the sequence in which the plurality of registers receive results from the first unit, the control means being responsive to the queue for selecting one of the plurality of registers.
Claim 11
Dependent Claim
265 words
In a pipeline data processing machine having first unit for execution of instructions running according to a first pipeline and a second unit including a high speed cache and a main store for storing data from a plurality of ports running according to a second pipeline, the high speed cache storing lines of data from the main store for quick access by the first unit, the first unit having a result register for holding results of the flow of the first pipeline and means for supplying addresses for the results, an apparatus for transferring the results in the result register to the high speed cache, comprising: a plurality of registers connected to receive results from the result register and to supply the results to the high speed cache, each of the plurality of registers including means for storing the result from at least one flow of the first pipeline, means for storing address information for the result of the at least one flow of the first pipeline, and means for storing control information for the register; and control means, in communication with the second unit and the plurality of registers, responsive to the control information and a flow of the second pipeline for selecting one of the registers as a port to the second unit and for updating the control information including means for maintaining a first-in, first-out queue for the plurality of registers identifying the sequence in which the plurality of registers receive results from the first unit, the control means being responsive to the queue for selecting one of the plurality of registers.
Claim 12
Dependent Claim
65 words
The apparatus of claim 9, further including means, responsive to the detection of a missing line, for generating a signal to cause a move-in of the missing line into the high speed cache from the main store; and means, responsive to a move-in of a line, for initiating a transfer of the results from one of the plurality of registers to the high speed cache.
Claim 13
Dependent Claim
108 words
The apparatus of claim 9, wherein the main store includes means for storing a change identifier with each page of data, each page including a plurality of lines of data, in the main storage system indicating changes to the page, the control means further including: means for generating a set change identifier signal in response to the storage of a result from one of the plurality of registers to the high speed cache; means in communication with the main store for setting the change identifier on a page corresponding to the result from the one register; and means for signaling the control means when the identifier is set.
Claim 14
Dependent Claim
86 words
The apparatus of claim 9, wherein the plurality of ports includes at least one port from which a request to fetch a line of data from the high speed cache is initiated; the apparatus further including: means for comparing an address of a fetch from the at least one port with addresses stored in the plurality of registers; means responsive to a match for disabling the fetch pending a transfer of results in the plurality of registers having a matching address to the high speed cache.
Claim 15
Dependent Claim
49 words
The apparatus of claim 9, further including: means, in communication with each of the plurality of registers, for determining whether a result in a given register resides in a line from the main store that is present in the high speed cache or missing from the high speed cache.
Claim 16
Dependent Claim
53 words
The apparatus of claim 9, wherein the results in the result register include up to a number N bits of data, and each of the plurality of registers is capable of storing up to a multiple M times N bits whereby more than one result can be stored in each of the registers.
Claim 17
Dependent Claim
70 words
The apparatus of claim 9, wherein the address information includes a system address portion necessary for accessing a line in the main store and an effective address portion necessary for accessing the line in the high speed cache and wherein the control means further includes means in communication with the main store controller for storing the system address portion of the address information for each of the plurality of registers.
References Cited (Backward Citations)
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