Resynchronization of a superscalar processor

Claim 3

A method as in claim 1, wherein the step of redirecting the in-order sequence of instruction fetching includes the step of redirecting fetching to the instruction preceding the instruction for which a resynchronization condition is detected.

Claim 4

A method as in claim 1, wherein the step of redirecting the in-order sequence of instruction fetching includes the step of redirecting fetching to the instruction for which a resynchronization condition is detected.

Claim 5

A method as in claim 1, wherein: the step of queuing the fetched instructions in-order includes the sub-steps of: queuing the instructions in-order in a reorder buffer having a plurality of reorder buffer entries; and selectively issuing the instructions among ones of a plurality of functional units to subsequently execute the instructions, the plurality of functional units each having a respective reservation station; further queuing the selected instructions directed to the functional units in the respective reservation station; and the step of flushing the queue of fetched instructions includes the sub-steps of: clearing the reservation stations of the plurality of functional units; and clearing all reorder buffer entries queued subsequent to the instruction for which the resynchronization condition is detected.

Claim 6

A method as in claim 1, wherein: the instructions include a data rotate instruction or data shift instruction which respectively rotate or shift data a variable number of bits, the variable number depending on a result of an instruction of preceding order; the instructions include a conditional branch instruction which is conditional upon a result of the data rotate instruction or data shift instruction; and the step of detecting a resynchronization condition includes the step of detecting a result of the data rotate instruction or data shift instruction setting the variable number of bits for rotating or shifting zero and a conditional branch instruction is conditional upon the result.

Claim 7

A method as in claim 1, wherein: the instructions include a floating point instruction for which a floating point exception condition is detected; the processor includes an input pin coupled to an external signal that determines whether the floating point exception condition is ignored; and the step of detecting a resynchronization condition includes the step of detecting a floating point exception condition and the external signal specifies that the floating point exception condition is ignored.

Claim 8

A method as in claim 1, wherein: the instructions include an instruction which is executed as a sequence of a plurality of suboperations; and the step of detecting a resynchronization condition includes the step of detecting, during execution of one of the plurality of suboperations, a condition which moots execution of subsequent suboperations.

Claim 9

A method as in claim 1, wherein: the instructions include a floating point instruction which is executed as a sequence of suboperations, the floating point instruction being executed by a floating point functional unit; and the step of detecting a resynchronization condition includes the step of detecting, during execution of a floating point suboperation, a condition which moots execution of subsequent suboperations.

Claim 10

A method as in claim 1, wherein: the instructions include floating point stack exchange instructions; and the step of detecting a resynchronization condition includes the step of detecting a stack error condition including a stack overflow condition and stack underflow condition during execution of a floating point stack exchange instruction.

Claim 11

A method as in claim 1, wherein: the instructions include a data store-to-memory instruction; and the step of detecting a resynchronization condition includes the step of detecting a store to instruction memory during execution of a data store-to-memory instruction.

Claim 12

A pipeline processor comprising: a fetch program counter for determining an in-order sequence of instruction fetching; an instruction cache coupled to the fetch program counter for fetching the instructions in-order; a reorder buffer array coupled to the instruction cache for queuing the fetched instructions in-order; a functional unit coupled to the instruction cache and coupled to the reorder buffer array for speculatively executing the instructions out-of-order to generate results; a reorder buffer controller coupled to the functional unit for retiring executed instruction results in-order; an instruction pointer coupled to the reorder buffer controller for tracking the retiring of executed instruction results; a resynchronization condition detector coupled to the functional unit for detecting a resynchronization condition as an instruction is executed; and a resynchronization controller coupled to the reorder buffer controller responsive to retiring of the result of an instruction for which a resynchronization condition is detected, the resynchronization controller further including: a queue controller coupled to the resynchronization controller for flushing the queue of fetched instructions; and a branch unit coupling the instruction pointer to the fetch program counter for redirecting the in-order sequence of instruction fetching based on the tracking of retired instruction results.

Claim 13

A pipeline processor comprising: a fetch program counter for determining an in-order sequence of instruction fetching; an instruction cache coupled to the fetch program counter for fetching the instructions in-order; a reorder buffer array coupled to the instruction cache for queuing the fetched instructions in-order; a functional unit coupled to the instruction cache and coupled to the reorder buffer array for speculatively executing the instructions out-of-order to generate results; a reorder buffer controller coupled to the functional unit for retiring executed instruction results in-order; an instruction pointer coupled to the reorder buffer controller for tracking the retiring of executed instruction results; a resynchronization condition detector coupled to the functional unit for detecting a resynchronization condition as an instruction is executed; and a resynchronization controller coupled to the reorder buffer controller responsive to retiring of the result of an instruction for which a resynchronization condition is detected, the resynchronization controller further including: a queue controller coupled to the resynchronization controller for flushing the queue of fetched instructions; and a branch unit coupling the instruction pointer to the fetch program counter for redirecting the in-order sequence of instruction fetching based on the tracking of retired instruction results.

Claim 14

A processor as in claim 11, further comprising: a plurality of functional units, ones of the plurality of functional units being selected to speculatively execute the instructions, the functional units having reservation stations for queuing the selected instructions; wherein the queue controller flushes the instruction queue by directing the plurality of functional units to flush the reservation stations and by directing the reorder buffer to flush the reorder buffer array.

Claim 15

A processor as in claim 11, further comprising: a plurality of functional units and wherein: a first functional unit is an arithmetic logic unit (ALU) and the instructions executed by the ALU include a data rotate instruction and a data shift instruction which respectively rotate or shift data a variable number of bits, the variable number depending on a result of an instruction of preceding order; a second functional unit is a branch unit and the instructions executed on the branch unit include a conditional branch instruction which is conditional upon a result of the data rotate instruction or data shift instruction; the branch unit including a circuit for generating a resynchronization condition signal when the first functional unit result setting the variable number of bits for rotating or shifting is zero.

Claim 16

A processor as in claim 11, wherein: the processor includes an input pin coupled to an external signal that determines whether a floating point exception condition is ignored; and the functional unit is a floating point unit and the instructions executed on the floating point unit include a floating point instruction for which a floating point exception condition is detected; the floating point unit including a circuit for generating a resynchronization condition signal when a floating point exception condition is detected and the external signal specifies that the floating point exception condition is ignored.

Claim 17

A processor as in claim 11, wherein: the functional unit is a functional unit that executes an instruction which is executed as a sequence of a plurality of suboperations; the functional unit including a circuit for generating a resynchronization condition signal during execution of one of the plurality of suboperations which moots execution of subsequent suboperations.

Claim 18

A processor as in claim 11, wherein: the functional unit is a floating point unit and instructions executed on the floating point unit include a floating point instruction which is executed as a sequence of suboperations, the floating point unit including a circuit for generating a resynchronization condition signal during execution of a floating point suboperation which moots execution of subsequent suboperations.

Claim 19

A processor as in claim 11, wherein: the instructions include a floating point stack exchange instruction; and the processor further includes a circuit for detecting stack error conditions including a stack overflow condition and stack underflow condition during execution of a floating point stack exchange instruction and generating a resynchronization condition signal when a stack error condition is detected.

Claim 20

A processor as in claim 11, wherein: the functional unit is a load/store functional unit; the instructions include a data store-to-memory instruction which is executed by the load/store functional unit; and the load/store functional unit includes a circuit for detecting a store to instruction memory during execution of a data store-to-memory instruction and generating a resynchronization condition signal when a store to instruction memory is detected.

Claim 21

A processor as in claim 11, wherein the resynchronization controller selectively redirects the in-order sequence of instruction fetching to the instruction preceding the instruction for which a resynchronization condition is detected in a first case and redirects the in-order sequence of instruction fetching to the instruction for which a resynchronization condition is detected in a second case.

Claim 24

A method as in claim 20, wherein: the instructions include a data rotate instruction and a data shift instruction which respectively rotate and shift data a variable number of bits, the variable number depending on a result of a previously dispatched instruction; the instructions include a conditional branch instruction which is conditional upon the result of the data rotate instruction and data shift instruction; and the step of detecting a resynchronization condition includes the step of detecting a result of the data rotate instruction or data shift instruction setting the variable number of bits for rotating or shifting zero and a conditional branch instruction is conditional upon the result.

Claim 25

A method as in claim 20, wherein: the instructions include a floating point instruction for which floating point exception conditions are detected; the processor includes an input pin coupled to an external signal that determines whether the floating point exception condition is ignored; and the step of detecting a resynchronization condition includes the step of detecting a floating point exception condition and the external signal specifies that the floating point exception condition is ignored.

Claim 26

A method as in claim 20, wherein: the instructions include an instruction which is dispatched and executed as a sequence of a plurality of suboperations; and the step of detecting a resynchronization condition includes the step of detecting, execution of a suboperation which moots execution of a subsequent suboperation.

Claim 27

A method as in claim 20, wherein: the instructions include a floating point instruction which is dispatched and executed as a sequence of suboperations; and the step of detecting a resynchronization condition includes the step of detecting, during execution of a floating point suboperation, a condition which moots execution of a subsequent suboperation.

Claim 28

A method as in claim 20, wherein: the instructions include a stack exchange instruction; and the step of detecting a resynchronization condition includes the step of detecting a stack error condition including a stack overflow condition and stack underflow condition during execution of a stack exchange instruction.

Claim 29

A method as in claim 20, wherein: the instructions include a floating point stack exchange instruction; and the step of detecting a resynchronization condition includes the step of detecting a stack error condition including a stack overflow condition and stack underflow condition during execution of a floating point stack exchange instruction.

Claim 30

A method as in claim 20, wherein: the instructions include a data store-to-memory instruction; and the step of detecting a resynchronization condition includes the step of detecting a store to instruction memory during execution of a data store-to-memory instruction.

Claim 31

A pipeline processor comprising: an instruction cache including: a cache memory; a fetch program counter register; and fetching logic coupled to the fetch program counter register and coupled to the cache memory; an instruction decoder coupled to the instruction cache; a plurality of functional units each coupled to the instruction decoder to receive instructions dispatched to designated ones of the functional units, each of the functional units having: a reservation station instruction queue; and instruction execution circuitry coupled to the reservation station instruction queue to receive an instruction for execution; a reorder buffer coupled to the instruction decoder and coupled to the functional units, including: an in-order queue of result entries coupled to the functional units to receive an execution result; retiring logic coupled to the head of the result entry queue to retire a result; and an instruction pointer coupled to the retiring logic, the instruction pointer coinciding with the fetch program counter of a retiring result; and resynchronization logic including: a plurality of resynchronization condition detectors coupled to designated ones of the functional units; a resynchronization indicator coupled to the reorder buffer queue of result entries; a queue controller coupled to the reorder buffer and responsive to the retiring logic and the resynchronization indicator by flushing the reorder buffer; queue logic coupled to the functional unit reservation stations and responsive to the retiring logic and the resynchronization indicator by flushing the reservation stations; and a target program counter responsive to the retiring logic and the resynchronization indicator by coupling the instruction pointer to the fetch program counter.

Claim 32

A pipeline processor comprising: an instruction cache including: a cache memory; a fetch program counter register; and fetching logic coupled to the fetch program counter register and coupled to the cache memory; an instruction decoder coupled to the instruction cache; a plurality of functional units each coupled to the instruction decoder to receive instructions dispatched to designated ones of the functional units, each of the functional units having: a reservation station instruction queue; and instruction execution circuitry coupled to the reservation station instruction queue to receive an instruction for execution; a reorder buffer coupled to the instruction decoder and coupled to the functional units, including: an in-order queue of result entries coupled to the functional units to receive an execution result; retiring logic coupled to the head of the result entry queue to retire a result; and an instruction pointer coupled to the retiring logic, the instruction pointer coinciding with the fetch program counter of a retiring result; and resynchronization logic including: a plurality of resynchronization condition detectors coupled to designated ones of the functional units; a resynchronization indicator coupled to the reorder buffer queue of result entries; a queue controller coupled to the reorder buffer and responsive to the retiring logic and the resynchronization indicator by flushing the reorder buffer; queue logic coupled to the functional unit reservation stations and responsive to the retiring logic and the resynchronization indicator by flushing the reservation stations; and a target program counter responsive to the retiring logic and the resynchronization indicator by coupling the instruction pointer to the fetch program counter.

Claim 33

A processor as in claim 28, wherein: a first functional unit is an arithmetic logic unit (ALU) and the instructions executed on the ALU include a data rotate instruction and a data shift instruction which respectively rotate or shift data a variable number of bits, the variable number depending on a result of an instruction of preceding order; a second functional unit is a branch unit and the instructions executed on the branch unit include a conditional branch instruction which is conditional upon a result of the data rotate instruction or data shift instruction; the branch unit including a circuit for generating a resynchronization condition signal when the first functional unit result setting the variable number of bits for rotating or shifting is zero.

Claim 34

A processor as in claim 28, wherein: the processor includes an input pin coupled to an external signal that determines whether a floating point exception condition is ignored; and a functional unit is a floating point unit and the instructions executed on the floating point unit include a floating point instruction for which a floating point exception condition is detected; the floating point unit including a circuit for generating a resynchronization condition signal when a floating point exception condition is detected and the external signal specifies that the floating point exception condition is ignored.

Claim 35

A processor as in claim 28, wherein: a functional unit is a functional unit that executes an instruction which is executed as a sequence of a plurality of suboperations; the functional unit including a circuit for generating a resynchronization condition signal during execution of one of the plurality of suboperations which moots execution of subsequent suboperations.

Claim 36

A processor as in claim 28, wherein: a functional unit is a floating point unit and instructions executed on the floating point unit include a floating point instruction which is executed as a sequence of suboperations, the floating point unit including a circuit for generating a resynchronization condition signal during execution of a floating point suboperation which moots execution of subsequent suboperations.

Claim 37

A processor as in claim 28, wherein: the instructions include a floating point stack exchange instruction; and the processor further includes a circuit for detecting stack error conditions including a stack overflow condition and stack underflow condition during execution of a floating point stack exchange instruction and generating a resynchronization condition signal when a stack error condition is detected.

Claim 38

A processor as in claim 28, wherein: a functional unit is a load/store functional unit; the instructions include a data store-to-memory instruction which is executed by the load/store functional unit; and the load/store functional unit includes a circuit for detecting a store to instruction memory during execution of a data store-to-memory instruction and generating a resynchronization condition signal when a store to instruction memory is detected.

Claim 39

A pipeline processor comprising: an instruction cache including: a cache memory; a fetch program counter register; and fetching logic coupled to the fetch program counter register and coupled to the cache memory, the fetching logic for updating the counter and fetching instructions designated by the fetch program counter; an instruction decoder coupled to the instruction cache for concurrently dispatching a plurality of instructions in the order of fetching; a plurality of functional units each coupled to the instruction decoder to receive dispatched instructions, the instructions being dispatched to designated ones of the functional units, each of the functional units having: a reservation station to queue the instructions; and instruction execution circuitry coupled to the reservation station to receive an instruction from the reservation station queue and to execute the instruction when execution of previously queued instructions is complete and data for executing the instruction is available from the execution of earlier dispatched instructions; a reorder buffer coupled to the instruction decoder and coupled to the functional units, the reorder buffer including: a queue of result entries, the entries being allocated in the order of dispatching and corresponding to the queued instructions, the entries receiving results from the functional units when execution of the corresponding instruction is complete; retiring logic coupled to the queue to retire result entries at the head of the queue; and an instruction pointer coupled to the retiring logic, the instruction pointer being updated by the retiring logic when the result entry is retired, the instruction pointer coinciding with the fetch program counter of the instruction corresponding to the result entry; and resynchronization logic including: a plurality of resynchronization condition detectors, each coupled to a designated functional unit, the resynchronization conditions being detected in association with an executing instruction; a resynchronization indicator coupled to the reorder buffer result entry queue, resynchronization being indicated when execution of the corresponding instructions is complete and a resynchronization condition is detected; a queue controller coupled to the reorder buffer and responsive to retiring the reorder buffer entry having a resynchronization indicator for flushing the reorder buffer; queue logic coupled to the functional unit reservation stations and responsive to retiring the reorder buffer entry having a resynchronization indicator for flushing the reorder buffer; and a target program counter coupling the instruction cache and reorder buffer to redirect the fetch program counter to the instruction addressed by the instruction pointer.

Claim 40

A pipeline processor comprising: an instruction cache including: a cache memory; a fetch program counter register; and fetching logic coupled to the fetch program counter register and coupled to the cache memory, the fetching logic for updating the counter and fetching instructions designated by the fetch program counter; an instruction decoder coupled to the instruction cache for concurrently dispatching a plurality of instructions in the order of fetching; a plurality of functional units each coupled to the instruction decoder to receive dispatched instructions, the instructions being dispatched to designated ones of the functional units, each of the functional units having: a reservation station to queue the instructions; and instruction execution circuitry coupled to the reservation station to receive an instruction from the reservation station queue and to execute the instruction when execution of previously queued instructions is complete and data for executing the instruction is available from the execution of earlier dispatched instructions; a reorder buffer coupled to the instruction decoder and coupled to the functional units, the reorder buffer including: a queue of result entries, the entries being allocated in the order of dispatching and corresponding to the queued instructions, the entries receiving results from the functional units when execution of the corresponding instruction is complete; retiring logic coupled to the queue to retire result entries at the head of the queue; and an instruction pointer coupled to the retiring logic, the instruction pointer being updated by the retiring logic when the result entry is retired, the instruction pointer coinciding with the fetch program counter of the instruction corresponding to the result entry; and resynchronization logic including: a plurality of resynchronization condition detectors, each coupled to a designated functional unit, the resynchronization conditions being detected in association with an executing instruction; a resynchronization indicator coupled to the reorder buffer result entry queue, resynchronization being indicated when execution of the corresponding instructions is complete and a resynchronization condition is detected; a queue controller coupled to the reorder buffer and responsive to retiring the reorder buffer entry having a resynchronization indicator for flushing the reorder buffer; queue logic coupled to the functional unit reservation stations and responsive to retiring the reorder buffer entry having a resynchronization indicator for flushing the reorder buffer; and a target program counter coupling the instruction cache and reorder buffer to redirect the fetch program counter to the instruction addressed by the instruction pointer.

Claim 41

A processor as in claim 35, wherein: a first functional unit is an arithmetic logic unit (ALU) and the instructions executed on the ALU include a data rotate instruction and a data shift instruction which respectively rotate or shift data a variable number of bits, the variable number depending on a result of an instruction of preceding order; a second functional unit is a branch unit and the instructions executed on the branch unit include a conditional branch instruction which is conditional upon a result of the data rotate instruction or data shift instruction; the branch unit including a circuit for generating a resynchronization condition signal when the first functional unit result setting the variable number of bits for rotating or shifting is zero.

Claim 42

A processor as in claim 35, wherein: the processor includes an input pin coupled to an external signal that determines whether a floating point exception condition is ignored; and a functional unit is a floating point unit and the instructions executed on the floating point unit include a floating point instruction for which a floating point exception condition is detected; the floating point unit including a circuit for generating a resynchronization condition signal when a floating point exception condition is detected and the external signal specifies that the floating point exception condition is ignored.

Claim 43

A processor as in claim 35, wherein: a functional unit is a functional unit that executes an instruction which is executed as a sequence of a plurality of suboperations; the functional unit including a circuit for generating a resynchronization condition signal during execution of one of the plurality of suboperations which moots execution of subsequent suboperations.

Claim 44

A processor as in claim 35, wherein: a functional unit is a floating point unit and instructions executed on the floating point unit include a floating point instruction which is executed as a sequence of suboperations, the floating point unit including a circuit for generating a resynchronization condition signal during execution of a floating point suboperation which moots execution of subsequent suboperations.

Claim 45

A processor as in claim 35, wherein: the instructions include a floating point stack exchange instruction; and the processor further includes a circuit for detecting stack error conditions including a stack overflow condition and stack underflow condition during execution of a floating point stack exchange instruction and generating a resynchronization condition signal when a stack error condition is detected.

Claim 46

A processor as in claim 35, wherein: a functional unit is a load/store functional unit; the instructions include a data store-to-memory instruction which is executed by the load/store functional unit; and the load/store functional unit includes a circuit for detecting a store to instruction memory during execution of a data store-to-memory instruction and generating a resynchronization condition signal when a store to instruction memory is detected.

Claim 47

A pipeline processor including a fetch program counter for determining an in-order sequence of instruction fetching, an instruction cache coupled to the fetch program counter for fetching the instructions in-order, a reorder buffer array coupled to the instruction cache for queuing the fetched instructions in-order, a functional unit coupled to the instruction cache and coupled to the reorder buffer array for speculatively executing the instructions out-of-order to generate results, a reorder buffer controller coupled to the functional unit for retiring executed instruction results in-order, an instruction pointer coupled to the reorder buffer controller for tracking the retiring of executed instruction results, the pipeline processor comprising: a resynchronization condition detector coupled to the functional unit for detecting a resynchronization condition as an instruction is executed; and a resynchronization controller coupled to the reorder buffer controller responsive to retiring of the result of an instruction for which a resynchronization condition is detected, the resynchronization controller further including: a queue controller coupled to the resynchronization controller for flushing the queue of fetched instructions; and a branch unit coupling the instruction pointer to the fetch program counter for redirecting the in-order sequence of instruction fetching based on the tracking of retired instruction results.

Claim 48

A pipeline processor including a fetch program counter for determining an in-order sequence of instruction fetching, an instruction cache coupled to the fetch program counter for fetching the instructions in-order, a reorder buffer array coupled to the instruction cache for queuing the fetched instructions in-order, a functional unit coupled to the instruction cache and coupled to the reorder buffer array for speculatively executing the instructions out-of-order to generate results, a reorder buffer controller coupled to the functional unit for retiring executed instruction results in-order, an instruction pointer coupled to the reorder buffer controller for tracking the retiring of executed instruction results, the pipeline processor comprising: a resynchronization condition detector coupled to the functional unit for detecting a resynchronization condition as an instruction is executed; and a resynchronization controller coupled to the reorder buffer controller responsive to retiring of the result of an instruction for which a resynchronization condition is detected, the resynchronization controller further including: a queue controller coupled to the resynchronization controller for flushing the queue of fetched instructions; and a branch unit coupling the instruction pointer to the fetch program counter for redirecting the in-order sequence of instruction fetching based on the tracking of retired instruction results.