US5056006A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Parallel processor with single program storage and sequencer and simultaneous instruction processing
Assignee: General Electric Co
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Filing: 1990-07-09
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Granted: 1991-10-08
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Expires: 2010-07-09
Abstract
Abstract A processor for use in CAT X-ray systems and NMR systems performs floating point arithmetic operations in parallel to shorten processing time. A single program memory and program sequencing unit operates a set of floating point arithmetic units to carry out parallel operations on data set storeed in respective data memories. An integer processor unit executes logical operations and a shared data memory stores constants and other data which is required by the integer processor unit and which is common to the operations performed by all of the floating point arithmetic units.
Inventors
- 👤 Kishore C. Acharya
- 👤 Paul C. Schanen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 22:48
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/76; G06F15/80; G06F15/8007; G06F15/8015
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
177 words
In a medical imaging system a digital processor for operating in a plurality of sets of acquired image data simultaneously, the combination comprising: a program memory for storing a program which directs the operation to be performed on each set of acquired image data; a program sequencing unit for reading the control program instructions from the program memory; a set of data memories for storing the respective sets of acquired image data; a shared data memory for storing data required in the processing of the acquire image data; and a set of processor units, each coupled to a respective one of the data memories and to the program memory and the shared data memory, each processor unit being operable to receive the program instructions read from the program memory by the program sequencing unit and in response to selected ones of the program instructions perform simultaneous operations on the acquired image data in the respective data memories, and in response to other selected ones of the program instructions simultaneously operate on data stored in the shared memory.
Claim 2
Dependent Claim
177 words
In a medical imaging system a digital processor for operating in a plurality of sets of acquired image data simultaneously, the combination comprising: a program memory for storing a program which directs the operation to be performed on each set of acquired image data; a program sequencing unit for reading the control program instructions from the program memory; a set of data memories for storing the respective sets of acquired image data; a shared data memory for storing data required in the processing of the acquire image data; and a set of processor units, each coupled to a respective one of the data memories and to the program memory and the shared data memory, each processor unit being operable to receive the program instructions read from the program memory by the program sequencing unit and in response to selected ones of the program instructions perform simultaneous operations on the acquired image data in the respective data memories, and in response to other selected ones of the program instructions simultaneously operate on data stored in the shared memory.
Claim 3
Dependent Claim
90 words
The digital processor all recited in claim 1 which includes a common processing unit that couples to the program memory and the shared data memory and being operable to receive the program instructions read from the program memory by the program sequencing unit, and in response to third selected ones of the program instructions, to perform logical operations that effect the processing of all the sets of acquired image data; and wherein each processor unit is responsive to the third selected ones of the program instructions to perform no operation.
Claim 4
Dependent Claim
73 words
The digital processor as recited in claim 1 in which each processor unit includes switch means which couples the processor unit to both the shared data memory and the processor unit's own data memory, and in which the switch means is operable in response to control program instructions read from the program memory to convey data between its processor unit and either the shared data memory or the processor unit's own data memory.
Claim 5
Dependent Claim
65 words
The digital processor as recited in claim 1 in which each processor unit includes both an FPU means and a coprocessor which collectively execute all of said selected ones of the program instructions and in which the FPU means executes one subset of said selected ones of the program instructions and the coprocessor executes a second subset of said selected ones of the program instructions.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-10-07 | 1995-04-08 | 1995-10-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-10-07 | 1999-04-08 | 1999-10-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-10-07 | 2003-04-08 | 2003-10-08 | $7700.00 | Window Closed / Lapsed |