US4736288A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Data processing device
Assignee: Hitachi Microcomputer System Ltd
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Filing: 1984-12-18
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Granted: 1988-04-05
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Expires: 2004-12-18
Abstract
Abstract A data processing device which is equipped with a plurality of arithmetic units so that a plurality of instructions may be processed in parallel by the plural arithmetic units. The device includes a register control circuit for assigning one of a plurality of physical registers to store instructions when more than one of the instructions requires the use of the same logical register. This correspondence between the physical and logical registers is maintained while instructions are subsequently transferred to the arithmetic units where they are processed in parallel.
Inventors
- 👤 Yooichi Shintani
- 👤 Tohru Shonai
- 👤 Shigeo Takeuchi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 23:29
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/76; G06F15/80; G06F15/8053; G06F15/8092
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
94 words
A data processing device comprising: a plurality of arithmetic units for processing a plurality of instructions in parallel; a plurality of first and second registers, for storing both data to be processed by said arithmetic units and the processed results of said arithmetic units; a control circuit for dynamically assigning different ones of said second registers to those instructions which designate an identical one of said first registers; and means maintaining the corresponding relationship between said first register and said assigned second registers while the instructions are processed in parallel in said arithmetic units.
Claim 2
Dependent Claim
94 words
A data processing device comprising: a plurality of arithmetic units for processing a plurality of instructions in parallel; a plurality of first and second registers, for storing both data to be processed by said arithmetic units and the processed results of said arithmetic units; a control circuit for dynamically assigning different ones of said second registers to those instructions which designate an identical one of said first registers; and means maintaining the corresponding relationship between said first register and said assigned second registers while the instructions are processed in parallel in said arithmetic units.
Claim 3
Dependent Claim
67 words
A data processing device according to claim 1, wherein said control circuit comprises: decode means for decoding said instructions; assigning means, responsive to said decode means, for assigning numbers of said first registers to corresponding numbers of said second registers; and control means, responsive to said decode means and said assigning means, for controlling transfer of data between said arithmetic units and said first and second registers.
Claim 4
Dependent Claim
125 words
A data processing device corresponding to claim 2, wherein said assigning means comprises: register status control means for indicating the status of said second registers; translation table control means, responsive to said register status control means and said decode means, for selecting one of said second registers to be newly assigned; translations table means, responsive to said translation table control means, for holding the numbers of said second registers corresponding to the numbers of said first registers which are selected by said translation table control means; and selector means, responsive to said translation table means, for selecting one of said second registers based on the outputs of said register status control means, said translation table control means, said translation table means and said decoder means.
Claim 5
Dependent Claim
137 words
A data processing device according to claim 3, wherein said selector means comprises: first selector means, responsive to the outputs of said translation table means and said decode means, for selecting the number of one of said second registers where a decoded instruction is to be stored; second selector means, responsive to the output of said decoder means and said translation table means, for selecting one of said second registers, from which the decoded instruction is to be read; third selector means, responsive to said register status control means and said second selector means, for selecting the arithmetic unit where the instruction will be processed; and fourth selector means, responsive to said register status control means and said second selector means, for detecting when information from a processing instruction is not available for processing the present instruction.
Claim 6
Dependent Claim
90 words
A data processing device according to claim 2, wherein said control means comprises: an arithmetic unit status control means for indicating the status of the arithmetic units, including an indication of which units are busy and the type of information from a particular instruction that is stored therein; and arithmetic unit selection means for monitoring the status of the arithmetic units, for signaling the decode means when no arithmetic units are available and for outputting the number of the arithmetic unit that is available to the register status control means.
Claim 7
Dependent Claim
115 words
A data processing device comprising: means for inputting instructions; a plurality of registers; detecting means for detecting when more than one of said instructions requires the use of the same one of said plurality of registers; assigning means, responsive to said detecting means, for dynamically assigning a different one of said plurality of registers to store one of the instructions when said same one of said plurality of registers is being used for another instruction; transfer means, responsive to said assigning means, for transferring data to selected ones of a plurality of arithmetic units; and control means, responsive to said assigning means, for controlling said arithmetic units such that the instructions are processed in parallel.
Claim 8
Dependent Claim
115 words
A data processing device comprising: means for inputting instructions; a plurality of registers; detecting means for detecting when more than one of said instructions requires the use of the same one of said plurality of registers; assigning means, responsive to said detecting means, for dynamically assigning a different one of said plurality of registers to store one of the instructions when said same one of said plurality of registers is being used for another instruction; transfer means, responsive to said assigning means, for transferring data to selected ones of a plurality of arithmetic units; and control means, responsive to said assigning means, for controlling said arithmetic units such that the instructions are processed in parallel.
Claim 9
Dependent Claim
106 words
A data processing device comprising: means for inputting instructions; a plurality of registers; detecting means for detecting when more than one of said instructions requires the use of the same one of said plurality of registers; assigning means, responsive to said means for detecting, for dynamically assigning a different one of said plurality of registers to store one of the instructions when said same one of said plurality of registers is being used for another instruction; and control means for controlling the transfer of data between said means for assigning and one of a plurality of arithmetic units such that said instructions are processed in parallel.
Claim 10
Dependent Claim
106 words
A data processing device comprising: means for inputting instructions; a plurality of registers; detecting means for detecting when more than one of said instructions requires the use of the same one of said plurality of registers; assigning means, responsive to said means for detecting, for dynamically assigning a different one of said plurality of registers to store one of the instructions when said same one of said plurality of registers is being used for another instruction; and control means for controlling the transfer of data between said means for assigning and one of a plurality of arithmetic units such that said instructions are processed in parallel.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-04-05 | 1991-10-05 | 1992-04-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-04-05 | 1995-10-05 | 1996-04-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-04-05 | 1999-10-05 | 2000-04-05 | $7700.00 | Window Closed / Lapsed |