US3787673A
Expired / Lapsed
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Pipelined high speed arithmetic unit
Assignee: Texas Instruments Inc
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Filing: 1972-04-28
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Granted: 1974-01-22
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Expires: 1992-04-28
Abstract
Abstract A digital computer central processing unit is disclosed having an arithmetic unit which forms an element of an instruction processing pipeline. The arithmetic unit has within it a plurality of arithmetic subunits each with its own storage and partitioned on a functional basis for the simultaneous execution of a plurality of arithmetic steps within the arithmetic unit while a plurality of instructions are simultaneously processed in their flow to the arithmetic unit. The sections of the arithmetic unit are accessible to operand input channels, the arithmetic unit further being partitioned for simultaneous single length operand execution or for double length operand execution.
Inventors
- 👤 W Watson
- 👤 C Stephenson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-22 16:45
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3885
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
109 words
In a digital computer arithmetic unit synchronized by a clock, the combination comprising: a. a plurality of parallel arithmetic sections each including a plurality of special purpose units, said special purpose units capable of performing different operations on input operands, b. means for connecting selected ones of said special purpose units in each said arithmetic section in series configurations in dependence on instructions therein, and c. means for synchronously feeding said operands through said series configurations of said arithmetic sections wherein said selected ones of said special purpose units simultaneously operate upon different operands during each clock period to provide periodic outputs in accordance with said arithmetic function instructions.
Claim 2
Dependent Claim
109 words
In a digital computer arithmetic unit synchronized by a clock, the combination comprising: a. a plurality of parallel arithmetic sections each including a plurality of special purpose units, said special purpose units capable of performing different operations on input operands, b. means for connecting selected ones of said special purpose units in each said arithmetic section in series configurations in dependence on instructions therein, and c. means for synchronously feeding said operands through said series configurations of said arithmetic sections wherein said selected ones of said special purpose units simultaneously operate upon different operands during each clock period to provide periodic outputs in accordance with said arithmetic function instructions.
Claim 3
Dependent Claim
97 words
In a digital computer arithmetic unit, the combination comprising: a. a plurality of special purpose units each capable of performing a different arithmetic operation on vector input signals, b. means for connecting selected ones of said special purpose units in series configurations in dependence upon instructions therein, and c. means for synchronously feeding vector input signals sequentially through said series configurations for simultaneous operations by said selected ones of said special purpose units upon different vector input signals during each synchronous period to provide a series of output signals operated upon according to said arithmetic function instruction.
Claim 4
Dependent Claim
97 words
In a digital computer arithmetic unit, the combination comprising: a. a plurality of special purpose units each capable of performing a different arithmetic operation on vector input signals, b. means for connecting selected ones of said special purpose units in series configurations in dependence upon instructions therein, and c. means for synchronously feeding vector input signals sequentially through said series configurations for simultaneous operations by said selected ones of said special purpose units upon different vector input signals during each synchronous period to provide a series of output signals operated upon according to said arithmetic function instruction.
Claim 5
Dependent Claim
78 words
The combination set forth in claim 2 wherein said plurality of special purpose units comprises: a. means for subtracting an exponent of said vector input signals, b. means for aligning said vector input signals, c. means for adding said vector input signals, d. means for multiplying said vector input signals, e. means for normalizing said vector input signals, f. means for accumulating said vector input signals, and g. means for outputing signals operated upon according to said instruction.
Claim 6
Dependent Claim
140 words
A pipelined arithmetic unit for a digital data processing system synchronized by a clock which comprises: a. a plurality of stages having structure for interconnections between said stages to form a multi-stage processing array for floating point addition of operands applied to said arithmetic unit, each said stage being partitionable into two parallel sections each having an add unit, b. a multiplier in each said section for producing on one clock pulse a pseudo sum and a pseudo carry in each said section, c. a programmable connection means for connecting the output of one said multiplier to said add unit on one said section, and d. a programmable connection means for connecting the output of the other said multiplier to the add unit in both said parallel sections, whereby single length or double length multiplication products selectively may be produced.
Claim 7
Dependent Claim
140 words
A pipelined arithmetic unit for a digital data processing system synchronized by a clock which comprises: a. a plurality of stages having structure for interconnections between said stages to form a multi-stage processing array for floating point addition of operands applied to said arithmetic unit, each said stage being partitionable into two parallel sections each having an add unit, b. a multiplier in each said section for producing on one clock pulse a pseudo sum and a pseudo carry in each said section, c. a programmable connection means for connecting the output of one said multiplier to said add unit on one said section, and d. a programmable connection means for connecting the output of the other said multiplier to the add unit in both said parallel sections, whereby single length or double length multiplication products selectively may be produced.
Claim 8
Dependent Claim
46 words
The combination set forth in claim 4 wherein said stages comprises an exponent subtract unit, an alignment unit, a normalizing unit, and an output unit in association with said add unit and wherein said multipliers serve to apply said sum and carry to said add unit.
Claim 9
Dependent Claim
38 words
The combination set forth in claim 4 wherein an instruction fetch unit, an instruction buffer unit and a control unit are connected in tandem for simultaneously processing a plurality of different instructions for execution by said arithmetic unit.
Claim 10
Dependent Claim
101 words
In a digital computer having an arithmetic unit formed by arithmetic sections formed of a plurality of special purpose units capable of performing different operations on input operands and means for connecting selected ones of said special purpose units in each said arithmetic section in series configurations, the method which comprises simultaneously but differently treating a plurality of said operands within said arithmetic unit under program instruction control to carry out an ordered predetermined sequence of operations on each said operand and simultaneously but differently treating a plurality of instructions in the instruction sequence immediately preceding execution by said arithmetic unit.
Claim 11
Dependent Claim
101 words
In a digital computer having an arithmetic unit formed by arithmetic sections formed of a plurality of special purpose units capable of performing different operations on input operands and means for connecting selected ones of said special purpose units in each said arithmetic section in series configurations, the method which comprises simultaneously but differently treating a plurality of said operands within said arithmetic unit under program instruction control to carry out an ordered predetermined sequence of operations on each said operand and simultaneously but differently treating a plurality of instructions in the instruction sequence immediately preceding execution by said arithmetic unit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-01-21 | 1977-07-23 | 1978-01-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-01-21 | 1981-07-23 | 1982-01-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-01-21 | 1985-07-23 | 1986-01-22 | $7700.00 | Window Closed / Lapsed |