US3684876A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Vector computing system as for use in a matrix computer
Assignee: Evans and Sutherland Computer Corp
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Filing: 1970-03-26
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Granted: 1972-08-15
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Expires: 1990-03-26
Abstract
Abstract A computing structure is disclosed for vector computation which structure is adaptable to accomplish mathematical solutions by iterative computation. Specifically, the structure includes first and second register means each of which is capable of registering a vector comprising a plurality of distinct components. Arithmetic means, e.g. a plurality of adders, is connected to each of the register means, for performing an arithmetic combination, e.g. determining the average value of similar components from the two register means. After each cycle, the arithmetic means transfers the results of its operative selectively to one or the other of the register means in accordance with the operation of a control unit. Control may be based upon a sequence of binary bits from an external source, or the signs or other signals developed in the course of computation or a combination thereof.
Inventors
- 👤 Ivan E Sutherland
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-22 18:13
CPC Classifications
G; G06; G06F; G06F17/00; G06F17/10; G06F17/16; G09; G09G; G09G1/00; G09G1/06; G09G1/08
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
223 words
A computing system comprising: a first register means including a plurality of first registers to register a first plurality of vector components; a second register means including a plurality of second registers to register a second plurality of vector components; means for providing signals in said first register means and said second register means representative respectively of said first and second pluralities of vector components; a plurality of arithmetic means, each for receiving signal representations from said first and second register means for arithmetically individually combining said first vector components from said first register means with said second vector components from second register means to provide signals representative of additive combinations of each of said first and second vector components; a plurality of gating means connected to each of said arithmetic means, at least one of said gating means including means for acting on received signals to divide representative values by a predetermined number; transfer means for transferring signals from said gating means connected to each of said arithmetic means, to one of said register means connected to such arithmetic means, to thereby replace the contents of such register means; and control means for controlling said transfer means, said arithmetic means and said gating means, to perform iterative computation on each of said vector components simultaneously until a stage of solution is attained.
Claim 2
Dependent Claim
223 words
A computing system comprising: a first register means including a plurality of first registers to register a first plurality of vector components; a second register means including a plurality of second registers to register a second plurality of vector components; means for providing signals in said first register means and said second register means representative respectively of said first and second pluralities of vector components; a plurality of arithmetic means, each for receiving signal representations from said first and second register means for arithmetically individually combining said first vector components from said first register means with said second vector components from second register means to provide signals representative of additive combinations of each of said first and second vector components; a plurality of gating means connected to each of said arithmetic means, at least one of said gating means including means for acting on received signals to divide representative values by a predetermined number; transfer means for transferring signals from said gating means connected to each of said arithmetic means, to one of said register means connected to such arithmetic means, to thereby replace the contents of such register means; and control means for controlling said transfer means, said arithmetic means and said gating means, to perform iterative computation on each of said vector components simultaneously until a stage of solution is attained.
Claim 3
Dependent Claim
42 words
A system according to claim 1 wherein said arithmetic means includes a plurality of adder units, each for receiving a component from each of said register means, and for providing signals representative of the average value of each of said components received.
Claim 4
Dependent Claim
39 words
A system according to claim 1 wherein said control means includes means to receive signals representative of the sign of at least one of said components registered in said register means to provide signals for controlling said transfer means.
Claim 5
Dependent Claim
39 words
A system according to claim 3 wherein said control means further includes means to logically test signals representative of the signs of certain of said components registered in said register means to provide signals to control said transfer means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-08-15 | 1976-02-14 | 1976-08-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-08-15 | 1980-02-14 | 1980-08-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-08-15 | 1984-02-14 | 1984-08-15 | $7700.00 | Window Closed / Lapsed |