Binary arithmetic and logic manipulator

Claim 2

A programmable logic and arithmetic manipulating arrangement comprising: a rectangular array of cells which define N+1columns of said cells and M rows of said cells, the output D of each cell in a row being applied as an input B to the next cell to the right in said row, the output E of each cell in a column being applied as an input C to the next lower cell in said column; a first storage stage U and a second storage stage V connected to each of said columns for determining the operation to be performed by each column, said U and V stages each being capable of assuming opposite binary states; a third storage stage X and a fourth storage stage Y connected to each of said cells for determining the operations to be performed by each of said cells in accordance with the operation determined by said U and V stages, said X and Y stages each being capable of assuming opposite binary states; means for applying respective B1-BM inputs to each of the cells in the leftmost column of said array; means for applying A1-AM respective inputs to the cells comprising each row in said array; means for applying respective C0-CN inputs to each of the cells in the topmost row of said array; said array being operative to produce respective D1-DM outputs from the cells comprising the rightmost column of said array and E0-EN respective outputs from the cells comprising the lowermost row of said array; said cells each comprising a circuit for producing the following D and E outputs: D X(YC+YB)+X(UA+UC(YB+YB)) E X(YB+YC)+X ((UV+UC+UC)(YB+ YB))+(UC(YB+YB))+(UVC)

Claim 3

A programmable logic and arithmetic manipulating arrangement comprising: a rectangular array of cells which define N+1 columns of said cells and M rows of said cells, the output D of each cell in a row being applied as an input B to the next cell to the right in said row, the output E of each cell in a column being applied as an input C to the next lower cell in said column; a first storage stage U and a second storage stage V connected to each of said columns for determining the operation to be performed by each column, said U and V stages each being capable of assuming opposite binary states; a third storage stage X and a fourth storage stage Y connected to each of said cells for determining the operations to be performed by each of said cells in accordance with the operation determined by said U and V stages, said X and Y stages each being capable of assuming opposite binary states; means for applying respective B1-BM inputs to each of the cells in the leftmost column of said array; means for applying A1-AM respective inputs to the cells comprising each row in said array; means for applying respective C0-CN inputs to each of the cells in the topmost row of said array; said array being operative to produce respective D1-DM outputs from the cells comprising the rightmost column of said array and E0-EN respective outputs from the cells comprising the lowermost row of said array; said cells each comprising a circuit for producing the following D and E outputs: D X(YC+YB)+XUA+UC(YB+YB)) E X(YB+YC)+X ((UV+UC+UC)(YB+ YB))+(UC(YB+YB))+(UVC) means for connecting the respective V stages, the U stages and the X and Y stages in series arrangement to enable said last named arrangement to be operated as a shift register in the column; and means for applying an input to each of said columns for respectively shifting the contents of said V, U, X and Y stages in the columns.

Claim 4

A programmable logic and arithmetic manipulating arrangement comprising: a rectangular array of cells which define N+1 columns of said cells and M rows of said cells, the output D of each cell in a row being applied as an input B to the next cell to the right in said row, the output E of each cell in a column being applied as an input C to the next lower cell in said column; a first storage stage U and a second storage stage V connected to each of said columns for determining the operation to be performed by each column, said U and V stages each being capable of assuming opposite binary states; a third storage stage X and a fourth storage stage Y connected to each of said cells for determining the operations to be performed by each of said cells in accordance with the operation determined by said U and V stages, said X and Y stages each being capable of assuming opposite binary states; means for applying respective B1-BM inputs to each of the cells in the leftmost column of said array; means for applying A1-AM respective inputs to the cells comprising each row in said array; means for applying respective C0-CN inputs to each of the cells in the topmost row of said array; said array being operative to produce respective D1-DM outputs from the cells comprising the rightmost column of said array and E0-EN respective outputs from the cells comprising the lowermost row of said array; said cells each comprising a circuit for producing the following D and E outputs: D X(YC+YB)+XUA+UC(YB+YB)) E X(YB+YC)+X ((UV+UC+UC)(YB+ YB))+(UC(YB+YB))+(UVC) means for connecting the respective V stages, the U stages and the X and Y stages in series arrangement to enable said last named arrangement to be operated as a shift register in the column; and means for applying an input to each of said columns for respectively shifting the contents of said V, U, X and Y stages in the columns.

Claim 5

A programmable logic and arithmetic manipulating arrangement comprising: a rectangular array of cells which define N+1 columns of said cells and M rows of said cells, the output D of each cell in a row being applied as an input B to the next cell to the right in said row, the output E of each cell in a column being applied as an input C to the next lower cell in said column; a first storage stage U and a second storage stage V connected to each of said columns for determining the operation to be performed by each column, said U and V stages each being capable of assuming opposite binary states, one binary state of said U stage resulting in an arithmetic operation for a column, the opposite binary state of said U stage resulting in a logical operation for said column, one binary state of said V stage resulting in the addition of a binary ''''1'''' to a column when the state of said U stage results in an arithmetic operation, the opposite binary state of said V stage in said arithmetic operation resulting in the addition of a binary ''''0'''' to a column, one binary state of said V stage resulting in an AND operation when the state of said U stage results in a logical operation, the opposite binary state of said V stage during said logical operation resulting in an OR operation; a third storage stage X and a fourth storage stage Y connected to each of said cells for determining the operations to be performed by each of said cells in accordance with the operation determinEd by said U and V stages, said X and Y stages each being capable of assuming opposite binary states; means for applying respective B1-BM inputs to each of the cells in the leftmost column of said array; means for applying A1-AM respective inputs to the cells comprising each row in said array; means for applying respective C0-CN inputs to each of the cells in the topmost row of said array; said array being operative to produce respective D1-DM outputs from the cells comprising the rightmost column of said array and E0-EN respective outputs from the cells comprising the lowermost row of said array; said cells each comprising a circuit for producing the following D and E outputs: D X(YC+YB)+X(UA+UC(YB+YB)) E X(YB+YC)+X ((UV+UC+UC)(YB+ YB))+(UC(YB+YB))+(UVC)

Claim 6

A programmable logic and arithmetic manipulating arrangement comprising: a rectangular array of cells which define N+1 columns of said cells and M rows of said cells, the output D of each cell in a row being applied as an input B to the next cell to the right in said row, the output E of each cell in a column being applied as an input C to the next lower cell in said column; a first storage stage U and a second storage stage V connected to each of said columns for determining the operation to be performed by each column, said U and V stages each being capable of assuming opposite binary states, one binary state of said U stage resulting in an arithmetic operation for a column, the opposite binary state of said U stage resulting in a logical operation for said column, one binary state of said V stage resulting in the addition of a binary ''''1'''' to a column when the state of said U stage results in an arithmetic operation, the opposite binary state of said V stage in said arithmetic operation resulting in the addition of a binary ''''0'''' to a column, one binary state of said V stage resulting in an AND operation when the state of said U stage results in a logical operation, the opposite binary state of said V stage during said logical operation resulting in an OR operation; a third storage stage X and a fourth storage stage Y connected to each of said cells for determining the operations to be performed by each of said cells in accordance with the operation determinEd by said U and V stages, said X and Y stages each being capable of assuming opposite binary states; means for applying respective B1-BM inputs to each of the cells in the leftmost column of said array; means for applying A1-AM respective inputs to the cells comprising each row in said array; means for applying respective C0-CN inputs to each of the cells in the topmost row of said array; said array being operative to produce respective D1-DM outputs from the cells comprising the rightmost column of said array and E0-EN respective outputs from the cells comprising the lowermost row of said array; said cells each comprising a circuit for producing the following D and E outputs: D X(YC+YB)+X(UA+UC(YB+YB)) E X(YB+YC)+X ((UV+UC+UC)(YB+ YB))+(UC(YB+YB))+(UVC)

Claim 7

A programmable logic and arithmetic manipulating arrangement comprising: a rectangular array of cells which define N+1 columns of said cells and M rows of said cells, the output D of each cell in a row being applied as an input B to the next cell to the right in said row, the output E of each cell in a column being applied as an input C to the next lower cell in said column; a first storage stage U and a second storage stage V connected to each of said columns for determining the operation to be performed by each column, said U and V stages each being capable of assuming opposite binary states; a third storage stage X and a fourth storage stage Y connected to each of said cells for determining the operations to be performed by each of said cells in accordance with the operation determined by said U and V stages, said X and Y stages each being capable of assuming opposite binary states, one binary state of said X stage resulting in a care operation in a cell controlled thereby, the opposite binary state of said X stage resulting in a don''t care operation in said cell, one binary state of said Y stage when the state of its corresponding X stage results in a care operation causing the selection of the true value of the B input to said cell, the opposite binary state of said Y stage during said care operation causing the selection of the complement of the B input to said cell, one binary state of said Y stage when the state of its corresponding X stage results in a don''t care operation causing a transfer operation in said cell, the opposite binary state of said Y stage during said don''t care operation causing a pass operation in said cell; means for applying respective B1-BM inputs to each of the cells in the leftmost column of said array; means for applying A1-AM respective inputs to the cells comprising each row in said array; means for applying respective C0-CN inputs to each of the cells in the topmost row of said array; said array being operative to produce respective D1-DM outputs from the cells comprising the rightmost column of said array and E0-EN respective outputs from the cells comprising the lowermost row of said array; said cells each comprising a circuit for producing the following D and E outputs: D X(YC+YB)+X(UA+UC(YB+YB)) E E X(YB+YC)+X ((UV+UC+UC)(YB+YB)+(UC(YB+YB))+(UVC)

Claim 8

A programmable logic and arithmetic manipulating arrangement comprising: a rectangular array of cells which define N+1 columns of said cells and M rows of said cells, the output D of each cell in a row being applied as an input B to the next cell to the right in said row, the output E of each cell in a column being applied as an input C to the next lower cell in said column; a first storage stage U and a second storage stage V connected to each of said columns for determining the operation to be performed by each column, said U and V stages each being capable of assuming opposite binary states; a third storage stage X and a fourth storage stage Y connected to each of said cells for determining the operations to be performed by each of said cells in accordance with the operation determined by said U and V stages, said X and Y stages each being capable of assuming opposite binary states, one binary state of said X stage resulting in a care operation in a cell controlled thereby, the opposite binary state of said X stage resulting in a don''t care operation in said cell, one binary state of said Y stage when the state of its corresponding X stage results in a care operation causing the selection of the true value of the B input to said cell, the opposite binary state of said Y stage during said care operation causing the selection of the complement of the B input to said cell, one binary state of said Y stage when the state of its corresponding X stage results in a don''t care operation causing a transfer operation in said cell, the opposite binary state of said Y stage during said don''t care operation causing a pass operation in said cell; means for applying respective B1-BM inputs to each of the cells in the leftmost column of said array; means for applying A1-AM respective inputs to the cells comprising each row in said array; means for applying respective C0-CN inputs to each of the cells in the topmost row of said array; said array being operative to produce respective D1-DM outputs from the cells comprising the rightmost column of said array and E0-EN respective outputs from the cells comprising the lowermost row of said array; said cells each comprising a circuit for producing the following D and E outputs: D X(YC+YB)+X(UA+UC(YB+YB)) E E X(YB+YC)+X ((UV+UC+UC)(YB+YB)+(UC(YB+YB))+(UVC)

Claim 9

A programmable logic and arithmetic manipulating arrangement comprising: a rectangular array of cells which define N+1 columns of said cells and M rows of said cells, the output D of each cell in a row being applied as an input B to the next cell to the right in said row, the oUtput E of each cell in a column being applied as an input C to the next lower cell in said column; a first storage stage U and a second storage stage V connected to each of said columns for determining the operation to be performed by each column, said U and V stages each being capable of assuming opposite binary states, one binary state of said U stage resulting in an arithmetic operation for a column, the opposite binary state of said U stage resulting in a logic operation for said column, one binary state of said V stage resulting in the addition of a binary ''''1'''' to a column when the state of said U stage results in an arithmetic operation, the opposite binary state of said V stage in said arithmetic operation resulting in the addition of a binary ''''0'''' to a column, one binary state of said V stage resulting in an AND operation when the state of said U stage results in a logical operation, the opposite binary state of said V stage during said logical operation resulting in an OR operation; a third storage stage X and a fourth storage stage Y connected to each of said cells for determining the operations to be performed by each of said cells in accordance with the operation determined by said U and V stages, said X and Y stages each being capable of assuming opposite binary states, one binary state of said X stage resulting in a care operation in a cell controlled thereby, the opposite binary state of said X stage resulting in a don''t care operation in said cell, one binary state of said Y stage when the state of its corresponding X stage results in a care operation causing the selection of the true value of the B input to said cell, the opposite binary state of said Y stage during said care operation causing the selection of the complement of the B input to said cell, one binary state of said Y stage when the state of its corresponding X stage results in a don''t care operation causing a transfer operation in said cell, the opposite binary state of said Y stage during said don''t care operation causing a pass operation in said cell; means for applying respective B1-BM inputs to each of the cells in the leftmost column of said array; means for applying A1-AM respective inputs to the cells comprising each row in said array; means for applying respective C0-DN inputs to each of the cells in the topmost row of said array; said array being operative to produce respective D1-DM outputs from the cells comprising the rightmost column of said array and E0-EN respective outputs from the cells comprising the lowermost row of said array; said cells each comprising a circuit for producing the following D and E outputs: D X(YC+YB)+X(UA+UC(YB+YB)) E X(YB+YC)+X ((UV+UC+UC)(YB+ YB))+(UC(YB+YB))+(UVC)

Claim 10

A programmable logic and arithmetic manipulating arrangement comprising: a rectangular array of cells which define N+1 columns of said cells and M rows of said cells, the output D of each cell in a row being applied as an input B to the next cell to the right in said row, the oUtput E of each cell in a column being applied as an input C to the next lower cell in said column; a first storage stage U and a second storage stage V connected to each of said columns for determining the operation to be performed by each column, said U and V stages each being capable of assuming opposite binary states, one binary state of said U stage resulting in an arithmetic operation for a column, the opposite binary state of said U stage resulting in a logic operation for said column, one binary state of said V stage resulting in the addition of a binary ''''1'''' to a column when the state of said U stage results in an arithmetic operation, the opposite binary state of said V stage in said arithmetic operation resulting in the addition of a binary ''''0'''' to a column, one binary state of said V stage resulting in an AND operation when the state of said U stage results in a logical operation, the opposite binary state of said V stage during said logical operation resulting in an OR operation; a third storage stage X and a fourth storage stage Y connected to each of said cells for determining the operations to be performed by each of said cells in accordance with the operation determined by said U and V stages, said X and Y stages each being capable of assuming opposite binary states, one binary state of said X stage resulting in a care operation in a cell controlled thereby, the opposite binary state of said X stage resulting in a don''t care operation in said cell, one binary state of said Y stage when the state of its corresponding X stage results in a care operation causing the selection of the true value of the B input to said cell, the opposite binary state of said Y stage during said care operation causing the selection of the complement of the B input to said cell, one binary state of said Y stage when the state of its corresponding X stage results in a don''t care operation causing a transfer operation in said cell, the opposite binary state of said Y stage during said don''t care operation causing a pass operation in said cell; means for applying respective B1-BM inputs to each of the cells in the leftmost column of said array; means for applying A1-AM respective inputs to the cells comprising each row in said array; means for applying respective C0-DN inputs to each of the cells in the topmost row of said array; said array being operative to produce respective D1-DM outputs from the cells comprising the rightmost column of said array and E0-EN respective outputs from the cells comprising the lowermost row of said array; said cells each comprising a circuit for producing the following D and E outputs: D X(YC+YB)+X(UA+UC(YB+YB)) E X(YB+YC)+X ((UV+UC+UC)(YB+ YB))+(UC(YB+YB))+(UVC)

Claim 11

An arrangement as defined in claim 5 wherein there are included a plurality of said arrays, the D1-DM outputs of an array being the B1-BM inputs to an array horizontally adjacent to said array, the E0-EN outputs of an array being the C0-CN inputs to an array horizontally adjacent to said array.

Claim 12

An arrangement as defined in claim 5 wherein said A and B inputs are tied together and said C and V inputs are tied together.

Claim 13

An arrangement as defined in claim 5 wherein there are included a plurality of said arrays, the E0-EN outputs of an array being the A1-AM inputs to another array.