Apparatus for handling out-of-order exceptions in pipe-lined parallel processing that prevents execution of all instructions behind exception predicted instruction and aborts if exception actually occurs

Claim 2

A parallel processing control apparatus comprising: a plurality of processing blocks each providing an equal function and incorporating pipeline operation units; a status register for storing processing status of each of said processing blocks; instruction feeding means for simultaneously allocating one instruction from a set of instructions with a predetermined order of execution to each of said processing blocks, respectively, according to a predetermined sequence of said processing blocks; exception prediction means for checking, in a first pipeline stage of an instruction, if said instruction may possibly cause an exception that at least one instruction overtakes an instruction which is ahead of said at least one instruction according to said predetermined order of execution; flagging means for setting a flag for a corresponding one of said processing blocks to indicate a possibility of said exception; flag holding means for holding the flag; and write decision means for writing the status of processing block when the processing block completes an instruction; wherein said write decision means continuously processes, if an instruction causes an exception, instructions that have been simultaneously allocated by said instruction feeding means with the instruction that caused the exception and are, according to said predetermined order of execution, positioned ahead of said instruction that caused the exception, aborts those instructions which are, according to said predetermined order of execution behind said instruction that caused the exception, and writes the status of the instruction that caused the exception in said status register, and wherein execution of all instructions which are, according to said predetermined order of execution of the instructions, positioned behind an instruction which is predicted to possibly cause an exception is prevented from being completed until execution of said instruction which is predicted to possibly cause an exception is completed.

Claim 3

The parallel processing control apparatus according to claim 1, wherein said write decision means selects, if plurality of said processing blocks simultaneously completed processing an instruction without causing an exception, a processing block without a flag which is positioned hindmost in said predetermined sequence among said plurality of processing blocks which have simultaneously completed processing of an instruction, and writes a result of execution of the instruction of the selected processing block into said status register.

Claim 4

The parallel processing control apparatus according to claim 1, wherein said write decision means continuously processes, if a plurality of instructions simultaneously cause exceptions, instructions that are positioned ahead of an foremost exception causing instruction which had been executed in a processing block that is positioned foremost in said predetermined sequence of processing blocks among the processing blocks in which exceptions have occurred, aborts those instructions which are positioned behind said foremost exception causing instruction including those instructions causing the exceptions, and writes the status of the processing block of the foremost exception causing instruction in said status register.

Claim 5

A parallel processing control apparatus comprising: a plurality of processing blocks each providing an equal function and incorporating pipeline operation units; a status register for storing processing status of each of said processing blocks; instruction feeding means for simultaneously allocating one instruction from a set of instructions with a predetermined order of execution to each of said processing blocks, respectively, according to a predetermined sequence of said processing blocks; exception prediction means for checking, in a first pipeline stage of an instruction, if said instruction may possibly cause an exception that at least one instruction overtakes an instruction which is ahead of said at least one instruction according to said predetermined order of execution; flagging means for setting a flag for a corresponding one of said processing blocks to indicate a possibility of said exception; flag holding means for holding the flag; and write decision means, wherein said write decision means selects, if plurality of said processing blocks simultaneously completed processing an instruction without causing an exception, a processing block without a flag which is positioned hindmost in said predetermined sequence among said plurality of processing blocks which have simultaneously completed processing of an instruction, and writes a result of execution of the instruction of the selected processing block into said status register, wherein said write decision means continuously processes, if an instruction causes an exception, instructions that have been simultaneously allocated by said instruction feeding means with the instruction that caused the exception and are, according to said predetermined order of execution, positioned ahead of said instruction that caused the exception, aborts those instructions which are, according to said predetermined order of execution behind said instruction that caused the exception, and writes the status of the instruction that caused the exception in said status register, and wherein said write decision means continuously processes, if a plurality of instructions simultaneously cause exceptions, instructions that are positioned ahead of an foremost exception causing instruction which had been executed in a processing block that is positioned foremost in said predetermined sequence among the processing blocks in which exceptions have occurred, aborts those instructions which are positioned behind said foremost exception causing instruction including those instructions causing the exceptions, and writes the status of the processing block of the foremost exception causing instruction in said status register, wherein execution of all instructions which are, according to said predetermined order of execution of the instructions, positioned behind an instruction which is predicted to possibly cause an exception is prevented from being completed until execution of said instruction which is predicted to possibly cause an exception is completed.

Claim 6

A parallel processing control apparatus comprising: a plurality of processing blocks each providing an equal function and incorporating pipeline operation units; a status register for storing processing status of each of said processing blocks; instruction feeding means for simultaneously allocating one instruction from a set of instructions with a predetermined order of execution to each of said processing blocks, respectively, according to a predetermined sequence of said processing blocks; exception prediction means for checking, in a first pipeline stage of an instruction, if said instruction may possibly cause an exception that at least one instruction overtakes an instruction which is ahead of said at least one instruction according to said predetermined order of execution; flagging means for setting a flag for a corresponding one of said processing blocks to indicate a possibility of said exception; flag holding means for holding the flag; and write decision means, wherein said write decision means selects, if plurality of said processing blocks simultaneously completed processing an instruction without causing an exception, a processing block without a flag which is positioned hindmost in said predetermined sequence among said plurality of processing blocks which have simultaneously completed processing of an instruction, and writes a result of execution of the instruction of the selected processing block into said status register, wherein said write decision means continuously processes, if an instruction causes an exception, instructions that have been simultaneously allocated by said instruction feeding means with the instruction that caused the exception and are, according to said predetermined order of execution, positioned ahead of said instruction that caused the exception, aborts those instructions which are, according to said predetermined order of execution behind said instruction that caused the exception, and writes the status of the instruction that caused the exception in said status register, and wherein said write decision means continuously processes, if a plurality of instructions simultaneously cause exceptions, instructions that are positioned ahead of an foremost exception causing instruction which had been executed in a processing block that is positioned foremost in said predetermined sequence among the processing blocks in which exceptions have occurred, aborts those instructions which are positioned behind said foremost exception causing instruction including those instructions causing the exceptions, and writes the status of the processing block of the foremost exception causing instruction in said status register, wherein execution of all instructions which are, according to said predetermined order of execution of the instructions, positioned behind an instruction which is predicted to possibly cause an exception is prevented from being completed until execution of said instruction which is predicted to possibly cause an exception is completed.

Claim 7

A parallel processing control apparatus for a processing system having a plurality of pipelined operating units having pipeline stages of a fetch stage, a decode stage, a plurality of execution stage and a write stage, said system successively issuing a plurality of instructions to said operating units in each clock period, said control apparatus comprising: a plurality of decision value holding means, each associated with different ones of said operating units for holding a plurality of position values, from a predetermined order of execution of instructions, of associated instructions issued to said associated operation unit among instructions that have been simultaneously issued to said plurality of operation units; a plurality of exception prediction means, each associated with different ones of said operating units for checking, in a third pipeline stage of processing said instruction, the possibility of causing an exception, wherein, upon detecting of the possibility of causing an exception by one of said exception prediction means, all said instructions issued after said instruction may caused exception are prevented from being completed until the completion of said instruction while any instruction issued prior to and simultaneously said instruction continuous to be executed; a plurality of flagging means, each associated with different ones of said of operation units and responsive to said plurality of exception prediction means, for setting a flag to indicate that prediction means of an associated operation unit does not predict an exception, that prediction means of at least one of the other operation predict an exception and that the position value of said at least one operating unit is larger than the position value of said associated operating unit, whereby the setting of said flag indicating the instruction executed by said associated operating unit has been overtaken; a plurality of flag holding means, each associated with different ones of said plurality of operating units, coupled to said associated flagging means, for holding the flag; and selection control means, responsive to said plurality of flag holding means, for selecting one of said operation units whose status is to be written in a status register when execution of an instruction is completed or when an exception actually occurs, wherein said selection control means writes the status of an operating unit into said status register if said operating unit completes an execution of an instruction without occurrence of an actual exception, and does not write the status of operating unit into said status register if a flag for the instruction is set to indicate that a status of another instruction that is behind the instruction is already written in the status register.

Claim 8

A parallel processing control apparatus for a processing system having a plurality of pipelined operating units having pipeline stages of a fetch stage, a decode stage, a plurality of execution stage and a write stage, said system successively issuing a plurality of instructions to said operating units in each clock period, said control apparatus comprising: a plurality of decision value holding means, each associated with different ones of said operating units for holding a plurality of position values, from a predetermined order of execution of instructions, of associated instructions issued to said associated operation unit among instructions that have been simultaneously issued to said plurality of operation units; a plurality of exception prediction means, each associated with different ones of said operating units for checking, in a third pipeline stage of processing said instruction, the possibility of causing an exception, wherein, upon detecting of the possibility of causing an exception by one of said exception prediction means, all said instructions issued after said instruction may caused exception are prevented from being completed until the completion of said instruction while any instruction issued prior to and simultaneously said instruction continuous to be executed; a plurality of flagging means, each associated with different ones of said of operation units and responsive to said plurality of exception prediction means, for setting a flag to indicate that prediction means of an associated operation unit does not predict an exception, that prediction means of at least one of the other operation predict an exception and that the position value of said at least one operating unit is larger than the position value of said associated operating unit, whereby the setting of said flag indicating the instruction executed by said associated operating unit has been overtaken; a plurality of flag holding means, each associated with different ones of said plurality of operating units, coupled to said associated flagging means, for holding the flag; and selection control means, responsive to said plurality of flag holding means, for selecting one of said operation units whose status is to be written in a status register when execution of an instruction is completed or when an exception actually occurs, wherein said selection control means writes the status of an operating unit into said status register if said operating unit completes an execution of an instruction without occurrence of an actual exception, and does not write the status of operating unit into said status register if a flag for the instruction is set to indicate that a status of another instruction that is behind the instruction is already written in the status register.

Claim 9

The parallel operation control apparatus according to claim 5, wherein, if a plurality of instructions are simultaneously completed without an occurrence of an exception, said selection control means selects an instruction which is, according to said predetermined order of execution of the instructions, positioned hindmost among the simultaneously completed instructions according to values stored in said decision value holding means, and writes the status of the selected instruction into the status register, thereby excluding status of flagged instructions from being written into the status register.

Claim 10

The parallel processing control apparatus according to claim 5, wherein, if any instruction actually caused an exception, said selection control means continuously processes instructions that have been simultaneously issued with the instruction causing the exception and are determined to be, according to said predetermined order of execution, ahead of the instruction causing the exception according to values held in said decision value holding means, aborts those instructions that are behind the instruction causing the exception, writes the status of the instruction causing the exception into the status register, while if a plurality of instructions caused exceptions, said selection control means writes, into the status register, the status of one of the instructions causing the exceptions that is determined to be, according to said predetermined order of execution, foremost according to values stored in said decision value holding means, continuously processes instructions that are ahead of the foremost instruction causing the exception, and aborts all instructions that are behind the foremost instruction causing the exception.

Claim 11

A parallel processing control apparatus for a processing system having a plurality of pipelined operating units having pipeline stages of a fetch stage, a decode stage, a plurality of execution stage and a write stage, said system successively issuing a plurality of instructions to said operating units in each clock period, said control apparatus comprising: a plurality of decision value holding means, each associated with different ones of said operating units for holding a plurality of position values, from a predetermined order of execution of instructions, of associated instructions issued to said associated operation unit among instructions that have been simultaneously issued to said plurality of operation units; a plurality of exception prediction means, each associated with different ones of said operating units for checking, in a third pipeline stage of processing said instruction, the possibility of causing an exception, wherein, upon detecting of the possibility of causing an exception by one of said exception prediction means, all said instructions issued after said instruction may caused exception are prevented from being completed until the completion of said instruction while any instruction issued prior to and simultaneously said instruction continuous to be executed; a plurality of flagging means, each associated with different ones of said of operation units and responsive to said plurality of exception prediction means, for setting a flag to indicate that prediction means of an associated operation unit does not predict an exception, that prediction means of at least one of the other operation predict an exception and that the position value of said at least one operating unit is larger than the position value of said associated operating unit, whereby the setting of said flag indicating the instruction executed by said associated operating unit has been overtaken; a plurality of flag holding means, each associated with different ones of said plurality of operating units, coupled to said associated flagging means, for holding the flag; and selection control means, responsive to said plurality of flag holding means, for selecting one of said operation units whose status is to be written in a status register when execution of an instruction is completed or when an exception actually occurs, wherein said selection control means selects, if a plurality of instructions are simultaneously completed without an occurrence of an exception, an instruction which is, according to said predetermined order of execution of the instructions, positioned hindmost among the simultaneously completed instructions according to values stored in said decision value holding means, writes the status of the selected instruction into the status register, thereby excluding status of flagged instructions from being written into the status register, wherein said selection control means continuously processes, if any instruction actually caused an exception, instructions that have been simultaneously issued with the instruction causing the exception and are determined to be, according to said predetermined order of execution, ahead of the instruction causing the exception according to values held in said decision value holding means, aborts those instructions that are behind the instruction causing the exception, and writes the status of the instruction causing the exception into the status register, wherein said selection control means writes into the status register, if a plurality of instructions caused exceptions, the status of one of the instructions causing the exceptions that is determined to be, according to said predetermined order of execution, foremost according to values stored in said decision value holding means, continuously processes instructions that are ahead of the foremost instruction causing the exception, and aborts all instructions that are behind the foremost instruction causing the exception.

Claim 12

A parallel processing control apparatus for a processing system having a plurality of pipelined operating units having pipeline stages of a fetch stage, a decode stage, a plurality of execution stage and a write stage, said system successively issuing a plurality of instructions to said operating units in each clock period, said control apparatus comprising: a plurality of decision value holding means, each associated with different ones of said operating units for holding a plurality of position values, from a predetermined order of execution of instructions, of associated instructions issued to said associated operation unit among instructions that have been simultaneously issued to said plurality of operation units; a plurality of exception prediction means, each associated with different ones of said operating units for checking, in a third pipeline stage of processing said instruction, the possibility of causing an exception, wherein, upon detecting of the possibility of causing an exception by one of said exception prediction means, all said instructions issued after said instruction may caused exception are prevented from being completed until the completion of said instruction while any instruction issued prior to and simultaneously said instruction continuous to be executed; a plurality of flagging means, each associated with different ones of said of operation units and responsive to said plurality of exception prediction means, for setting a flag to indicate that prediction means of an associated operation unit does not predict an exception, that prediction means of at least one of the other operation predict an exception and that the position value of said at least one operating unit is larger than the position value of said associated operating unit, whereby the setting of said flag indicating the instruction executed by said associated operating unit has been overtaken; a plurality of flag holding means, each associated with different ones of said plurality of operating units, coupled to said associated flagging means, for holding the flag; and selection control means, responsive to said plurality of flag holding means, for selecting one of said operation units whose status is to be written in a status register when execution of an instruction is completed or when an exception actually occurs, wherein said selection control means selects, if a plurality of instructions are simultaneously completed without an occurrence of an exception, an instruction which is, according to said predetermined order of execution of the instructions, positioned hindmost among the simultaneously completed instructions according to values stored in said decision value holding means, writes the status of the selected instruction into the status register, thereby excluding status of flagged instructions from being written into the status register, wherein said selection control means continuously processes, if any instruction actually caused an exception, instructions that have been simultaneously issued with the instruction causing the exception and are determined to be, according to said predetermined order of execution, ahead of the instruction causing the exception according to values held in said decision value holding means, aborts those instructions that are behind the instruction causing the exception, and writes the status of the instruction causing the exception into the status register, wherein said selection control means writes into the status register, if a plurality of instructions caused exceptions, the status of one of the instructions causing the exceptions that is determined to be, according to said predetermined order of execution, foremost according to values stored in said decision value holding means, continuously processes instructions that are ahead of the foremost instruction causing the exception, and aborts all instructions that are behind the foremost instruction causing the exception.