US4875160A
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US
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Method for implementing synchronous pipeline exception recovery
Assignee: Hewlett Packard Development Co LP
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Filing: 1988-07-20
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Granted: 1989-10-17
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Expires: 2008-07-20
Abstract
Abstract Pipelined CPUs achieve high-performance by fine tuning the pipe stages to execute typical instruction sequences. Atypical instruction sequences result in pipeline exceptions. The disclosed method provides graceful exception handling and recovery in a micropipelined memory interface. The use of a memory reference restart command latch allows an implementation that requires no additional logic for conditional writing of states pending exception checking. The exception handling hardware is minimized because instructions which cause exceptions are never re-executed, and exception handling microcode executes in-line with the normal microcode flow.
Inventors
- 👤 John F. Brown, III
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 15:14
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/0703; G06F11/0793; G06F11/0706; G06F11/0721; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3861; G06F9/3863
Claims Analysis
Total Claims: 32
Claim 1
Independent Claim
203 words
A processor comprising: (a) an execution unit having a plurality of execution stages for accessing operands from local registers, performing operations on said operands, and for storing results of said operations; (b) a memory interface unit having a plurality of stages including a memory-request stage for receiving memory address from said execution unit and a memory-access stage for evaluating said memory address to determine if said memory address is available for access and for accessing a memory if said address is available or for issuing an exception control signal if said memory address is not available for access; (c) pipelining means for applying sets of control bits to each of said stages of said execution unit and to each of said memory-request stage and said memory-access stage of said memory interface unit in successive ones of machine cycles of the processor. (d) latch means for holding a set of said control bits applied to said memory-access stage of said memory interface unit when said exception control signal is issued in a given one of said machine cycles, and for thereafter re-applying said set of control bits to said memory-access stage in a subsequent one of said machine cycles after said given machine cycle.
Claim 2
Dependent Claim
203 words
A processor comprising: (a) an execution unit having a plurality of execution stages for accessing operands from local registers, performing operations on said operands, and for storing results of said operations; (b) a memory interface unit having a plurality of stages including a memory-request stage for receiving memory address from said execution unit and a memory-access stage for evaluating said memory address to determine if said memory address is available for access and for accessing a memory if said address is available or for issuing an exception control signal if said memory address is not available for access; (c) pipelining means for applying sets of control bits to each of said stages of said execution unit and to each of said memory-request stage and said memory-access stage of said memory interface unit in successive ones of machine cycles of the processor. (d) latch means for holding a set of said control bits applied to said memory-access stage of said memory interface unit when said exception control signal is issued in a given one of said machine cycles, and for thereafter re-applying said set of control bits to said memory-access stage in a subsequent one of said machine cycles after said given machine cycle.
Claim 3
Dependent Claim
42 words
A processor according to claim 1 wherein said control bits are generated in a microinstruction store, and means are included for addressing said microinstruction store to produce a new microinstruction containing a set of control bits during each of said machine cycles.
Claim 4
Dependent Claim
27 words
A processor according to claim 2 wherein said addressing means is responsive to said exception control signal to cause addressing of a different sequence of said microinstruction.
Claim 5
Dependent Claim
26 words
A processor according to claim 3 wherein said different sequence of microinstructions functions to remove the condition which caused said exception control signal to be issued.
Claim 6
Dependent Claim
37 words
A processor according to claim 1 wherein said evaluating of said memory address includes tag comparison in a translation buffer and said exception control signal is issued when a match is not found in said tag comparison.
Claim 7
Dependent Claim
22 words
A processor according to claim 1 wherein said address-compare means is a translation buffer for storing page table entries for virtual addressing.
Claim 8
Independent Claim
208 words
A method of operating a processor comprising the steps of: (a) pipelining execution of instructions in an execution unit, the execution unit having a plurality of execution stages for accessing operands from local registers, performing operations on said operands, and for storing results of said operations, while, in parallel, pipelining execution of said instructions in a memory interface unit having a plurality of stages, including a memory-request stage for receiving memory addresses from said execution unit and including a memory-access stage for evaluating said memory addresses to determine if available for access and for sending said memory addresses to a memory for accessing if available or for issuing an exception control signal if not available; (b) applying sets of control bits generated in a microinstruction store to each of said stages of said execution unit and said memory interface unit in successive ones of machine cycles of the processor, (c) holding a set of said control bits applied to a later one of said stages of said memory interface unit when said exception control signal is issued in a given machine cycle, and thereafter re-applying said same set of control bits to said later stage in a subsequent one of said machine cycles after said given machine cycle.
Claim 9
Independent Claim
208 words
A method of operating a processor comprising the steps of: (a) pipelining execution of instructions in an execution unit, the execution unit having a plurality of execution stages for accessing operands from local registers, performing operations on said operands, and for storing results of said operations, while, in parallel, pipelining execution of said instructions in a memory interface unit having a plurality of stages, including a memory-request stage for receiving memory addresses from said execution unit and including a memory-access stage for evaluating said memory addresses to determine if available for access and for sending said memory addresses to a memory for accessing if available or for issuing an exception control signal if not available; (b) applying sets of control bits generated in a microinstruction store to each of said stages of said execution unit and said memory interface unit in successive ones of machine cycles of the processor, (c) holding a set of said control bits applied to a later one of said stages of said memory interface unit when said exception control signal is issued in a given machine cycle, and thereafter re-applying said same set of control bits to said later stage in a subsequent one of said machine cycles after said given machine cycle.
Claim 10
Dependent Claim
38 words
A method according to claim 7 including the step of generating said sets of control bits by addressing said microinstruction store to produce a new microinstruction containing a set of control bits during each of said machine cycles.
Claim 11
Dependent Claim
29 words
A method according to claim 8 wherein said addressing of said microinstruction store is responsive to said exception control to cause addressing of a different sequence of said microinstructions.
Claim 12
Dependent Claim
25 words
A method according to claim 9 wherein said different sequence of microinstructions functions to remove the condition which caused said exception control to be issued.
Claim 13
Dependent Claim
23 words
A method according to claim 7 wherein said evaluating said addresses is by a translation buffer storing page table entries for virtual addressing.
Claim 14
Independent Claim
269 words
A method of operating a processor comprising the steps of: (a) executing pipelined instructions in an execution unit having a plurality of pipelined execution stages including a first stage for accessing operands from local registers, a second stage for performing operations on said operands, and a third stage for storing results of said operations; (b) while at the same time, in parallel, executing the same pipelined instructions in a memory interface unit having a plurality of pipelined stages including a memory request stage for receiving memory addresses from said execution unit, a memory-access stage for evaluating said memory addresses and for applying said memory addresses to memory access means if said evaluating indicates said memory address is available for access or for issuing an exception control signal if said evaluating indicates said memory address is not available for access; (c) generating from a microinstruction store sets of control bits, one set for each cycle of operation of said processor, pipelining said sets of control bits by applying at least some of each one of said sets of control bits to each said first, second and third stages of said execution unit and to each one of said memory-request and memory-access stages of said memory interface unit in successive ones of said machine cycles, (d) holding said set of control bits applied to said memory-access stage of said memory interface unit when said exception control signal is issued in a given one of said machine cycles, and thereafter re-applying said set of control bits to said memory-access stage in a later one of said machine cycles after said given one.
Claim 15
Independent Claim
269 words
A method of operating a processor comprising the steps of: (a) executing pipelined instructions in an execution unit having a plurality of pipelined execution stages including a first stage for accessing operands from local registers, a second stage for performing operations on said operands, and a third stage for storing results of said operations; (b) while at the same time, in parallel, executing the same pipelined instructions in a memory interface unit having a plurality of pipelined stages including a memory request stage for receiving memory addresses from said execution unit, a memory-access stage for evaluating said memory addresses and for applying said memory addresses to memory access means if said evaluating indicates said memory address is available for access or for issuing an exception control signal if said evaluating indicates said memory address is not available for access; (c) generating from a microinstruction store sets of control bits, one set for each cycle of operation of said processor, pipelining said sets of control bits by applying at least some of each one of said sets of control bits to each said first, second and third stages of said execution unit and to each one of said memory-request and memory-access stages of said memory interface unit in successive ones of said machine cycles, (d) holding said set of control bits applied to said memory-access stage of said memory interface unit when said exception control signal is issued in a given one of said machine cycles, and thereafter re-applying said set of control bits to said memory-access stage in a later one of said machine cycles after said given one.
Claim 16
Dependent Claim
35 words
A method according to claim 12 wherein said step of generating control bits includes addressing said microinstruction store to produce a new microinstruction containing said set of control bits during each of said machine cycles.
Claim 17
Dependent Claim
30 words
A method according to claim 13 wherein said addressing of the microinstruction store is responsive to said exception control signal to cause addressing of a different sequence of said microinstructions.
Claim 18
Dependent Claim
26 words
A method according to claim 14 wherein said different sequence of microinstructions functions to remove the condition which caused said exception control signal to be issued.
Claim 19
Dependent Claim
32 words
A method according to claim 15 wherein said evaluating of memory addresses includes tag comparison and said exception control signal is issued when a match is not found in said tag comparison.
Claim 20
Dependent Claim
30 words
A method according to claim 12 wherein said step of re-applying said control bits is done while a non-operative set of control bits are applied to other of said stages.
Claim 21
Dependent Claim
24 words
A method according to claim 12 wherein said memory-access stage evaluates said addresses in a translation buffer storing page table entries for virtual addressing.
Claim 22
Dependent Claim
228 words
A processor comprising: (a) an execution unit having a plurality of execution stages including a first stage for accessing operands from local registers, a second stage for performing operations on said operands, and a third stage for storing results of said operations; (b) a memory interface unit having a plurality of stages including a memory-request stage for receiving a memory address, a memory-access stage for evaluating availability of said memory address for access and receiving data from memory if available or for issuing an exception control signal if said memory address is not available for access; (c) means for generating sets of control bits, one set for each machine cycle of operation of said processor, and pipelining means including clocking means for applying at least some of each one of said sets of control bits to each of said first, second and third stages of said execution unit and to each of said memory-request stage and said memory-access stage of said memory interface unit, in successive ones of said machine cycles, (d) latch means for holding said set of control bits applied to said memory-access stage of said memory interface unit when said exception control signal is issued in a given machine cycle, and for re-applying said set of control bits to said memory-access stage in a later one of said machine cycles after said given machine cycle.
Claim 23
Dependent Claim
228 words
A processor comprising: (a) an execution unit having a plurality of execution stages including a first stage for accessing operands from local registers, a second stage for performing operations on said operands, and a third stage for storing results of said operations; (b) a memory interface unit having a plurality of stages including a memory-request stage for receiving a memory address, a memory-access stage for evaluating availability of said memory address for access and receiving data from memory if available or for issuing an exception control signal if said memory address is not available for access; (c) means for generating sets of control bits, one set for each machine cycle of operation of said processor, and pipelining means including clocking means for applying at least some of each one of said sets of control bits to each of said first, second and third stages of said execution unit and to each of said memory-request stage and said memory-access stage of said memory interface unit, in successive ones of said machine cycles, (d) latch means for holding said set of control bits applied to said memory-access stage of said memory interface unit when said exception control signal is issued in a given machine cycle, and for re-applying said set of control bits to said memory-access stage in a later one of said machine cycles after said given machine cycle.
Claim 24
Dependent Claim
41 words
A processor according to claim 19 wherein said means for generating control bits includes a microinstruction store and means for addressing said microinstruction store to produce a new microinstruction containing said set of control bits during each of said machine cycles.
Claim 25
Dependent Claim
28 words
A processor according to claim 20 wherein said means for addressing is responsive to said exception control signal to cause addressing of a different sequence of said microinstructions.
Claim 26
Dependent Claim
26 words
A processor according to claim 21 wherein said different sequence of microinstructions functions to remove the condition which caused said exception control signal to be issued.
Claim 27
Dependent Claim
32 words
A processor according to claim 22 wherein said evaluating of memory address includes tag comparison and said exception control signal is issued when a match is not found in said tag comparison.
Claim 28
Dependent Claim
42 words
A processor according to claim 19 wherein said memory-access stage includes a translation buffer for storing page table entries for virtual addressing, and said evaluating includes determining if said memory address is within the range of any of said page table entries.
Claim 29
Dependent Claim
173 words
A processor comprising: (a) a pipelined execution unit having a plurality of pipeline stages, the execution unit including means providing memory addresses for memory access; (b) a pipelined memory access unit having a plurality of pipeline stages including memory-test means and memory-access means, said memory access unit receiving a memory address from said execution unit and testing said memory address in said memory-test means to issue an exception control signal if a selected condition is detected or accessing a memory by said memoryaccess means if said selected condition is not detected; (c) said execution unit and said memory access unit being controlled by sets of control bits received from a control store and applied to said pipeline stages in successive machine cycles of the processor; (d) and means for holding a set of control bits applied to said memory-access means if said exception control signal is issued in a given machine cycle, then re-applying said set of control bits to said memory-access means in a subsequent machine cycle after said given machine cycle.
Claim 30
Dependent Claim
173 words
A processor comprising: (a) a pipelined execution unit having a plurality of pipeline stages, the execution unit including means providing memory addresses for memory access; (b) a pipelined memory access unit having a plurality of pipeline stages including memory-test means and memory-access means, said memory access unit receiving a memory address from said execution unit and testing said memory address in said memory-test means to issue an exception control signal if a selected condition is detected or accessing a memory by said memoryaccess means if said selected condition is not detected; (c) said execution unit and said memory access unit being controlled by sets of control bits received from a control store and applied to said pipeline stages in successive machine cycles of the processor; (d) and means for holding a set of control bits applied to said memory-access means if said exception control signal is issued in a given machine cycle, then re-applying said set of control bits to said memory-access means in a subsequent machine cycle after said given machine cycle.
Claim 31
Dependent Claim
18 words
A processor according to claim 25 wherein said memory-test means includes a translation buffer holding page table entries.
Claim 32
Dependent Claim
36 words
A processor according to claim 25 wherein said control store includes addressing means and said exception control signal is received in said addressing means to cause a jump to a routine to remove said selected condition.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-10-16 | 1993-04-17 | 1993-10-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-10-16 | 1997-04-17 | 1997-10-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-10-16 | 2001-04-17 | 2001-10-17 | $7700.00 | Window Closed / Lapsed |