Method and system for storing and processing multiple memory addresses

Claim 3

The storing and processing system of claim 1, wherein the memory address processing unit comprises an address decoder.

Claim 4

The storing and processing system of claim 1 further comprising a latch having an input bus coupled to the output bus of the address pipeline to receive each one of the memory addresses stored in the address storage units and an output bus coupled to the memory address processing circuit to process a memory address stored in the latch.

Claim 5

The storing and processing system of claim 1 further comprising a plurality of address bus circuits each of which is coupled to a respective bit of the output bus, the bus circuits coupling the memory address from an enabled address storage unit to the memory address processing circuit.

Claim 6

The storing and processing system of claim 4 wherein the address bus circuits each comprises a latch having an input coupled to a respective bit of the output bus and an output coupled to the memory address processing circuit.

Claim 7

The storing and processing system of claim 1, further comprising an adder for allowing the storing and processing system to operate in a burst mode, the adder having an input bus coupled to the output bus of the address pipeline and an output bus coupled to the memory address processing circuit, the adder generating a series of addresses that increment from an initial address stored in the address pipeline.

Claim 8

The storing and processing system of claim 1 wherein the memory addresses stored in each of the address storage units of the address pipeline comprise respective addresses of columns of memory cell in at least one memory array.

Claim 9

A memory device, comprising: at least one array of memory cells adapted to store data at a location determined by a row address and a column address; a row address circuit adapted to select a row of memory cells in the array corresponding to a row address applied to the row address circuit; a column address circuit adapted to select a column of memory cells in the array corresponding to a column address applied to the column address circuit; a data path circuit adapted to couple data between an external terminal and a memory cell in the row and column of the array corresponding to the row and column address applied to the row address circuit and the column address circuit, respectively; a command buffer adapted to receive a memory command to control the operation of the memory device; an address buffer adapted to receive row addresses and column addresses applied to the address buffer; an address pipeline having an input bus coupled to the address buffer, and a plurality of address storage units each of which stores a respective address applied to the input bus responsive to a respective input enable signal, each of the address pipelines applying its stored address to an output bus of the address pipeline responsive to a respective output enable signal; a memory address processing circuit coupled to the output bus of the address pipeline; and a control circuit selectively applying the respective input enable signals and output enable signals to each of the address storage units.

Claim 10

A memory device, comprising: at least one array of memory cells adapted to store data at a location determined by a row address and a column address; a row address circuit adapted to select a row of memory cells in the array corresponding to a row address applied to the row address circuit; a column address circuit adapted to select a column of memory cells in the array corresponding to a column address applied to the column address circuit; a data path circuit adapted to couple data between an external terminal and a memory cell in the row and column of the array corresponding to the row and column address applied to the row address circuit and the column address circuit, respectively; a command buffer adapted to receive a memory command to control the operation of the memory device; an address buffer adapted to receive row addresses and column addresses applied to the address buffer; an address pipeline having an input bus coupled to the address buffer, and a plurality of address storage units each of which stores a respective address applied to the input bus responsive to a respective input enable signal, each of the address pipelines applying its stored address to an output bus of the address pipeline responsive to a respective output enable signal; a memory address processing circuit coupled to the output bus of the address pipeline; and a control circuit selectively applying the respective input enable signals and output enable signals to each of the address storage units.

Claim 11

The memory device of claim 8, wherein the memory address processing unit comprises an address decoder.

Claim 12

the memory device of claim 8 further comprising a latch having an input bus coupled to the output bus of the address pipeline to receive each one of the memory addresses stored in the address storage units and an output bus coupled to the memory address processing circuit to process a memory address stored in the latch.

Claim 13

The memory device of claim 8 further comprising a plurality of address bus circuits each of which is coupled to a respective bit of the output bus, the bus circuits coupling the memory address from an enabled address storage unit to the memory address processing circuit.

Claim 14

The memory device of claim 11 wherein the address bus circuits each comprises a latch having an input coupled to a respective bit of the output bus and an output coupled to the memory address processing circuit.

Claim 15

The memory device of claim 8, further comprising an adder for allowing the memory device to operate in a burst mode, the adder having an input bus coupled to the output bus of the address pipeline and an output bus coupled to the memory address processing circuit, the adder generating a series of addresses that increment from an initial address stored in the address pipeline.

Claim 16

The memory device of claim 8 wherein the memory addresses stored in each of the address storage units of the address pipeline comprise respective addresses of columns of memory cells in the array of memory cells.

Claim 17

A memory device, comprising: at least one array of memory cells adapted to store data at a location determined by a tow address and a column address; a row address circuit adapted to select a row of memory cells in the array corresponding to a row address applied to the row address circuit; a column address circuit adapted to select a column of memory cells in the array corresponding to a column address applied to the column address circuit; a data path circuit adapted to couple data between an external terminal and a memory cell in the row and column of the array corresponding to the row and column address applied to the row address circuit and the column address circuit, respectively; a command buffer adapted to receive a plurality of command packets each of which contain a plurality of command words, at least one of the command words containing at least one memory address; at least one command word register coupled to the command buffer, the command words being transferred from the command buffer to the command word register after the predetermined number of command words have been stored in the command buffer; an address pipeline having an input bus coupled to the command word register, the address pipeline having a plurality of address storage units each of which stores a respective memory address applied to the input bus responsive to a respective input enable signal, each of the address storage units applying its stored address to an output bus of the address pipeline responsive to a respective output enable signal; a control circuit selectively applying the respective input enable signals and output enable signals to each of the address storage units; and a memory address processing circuit coupled to the output bus of the address pipeline.

Claim 18

A memory device, comprising: at least one array of memory cells adapted to store data at a location determined by a tow address and a column address; a row address circuit adapted to select a row of memory cells in the array corresponding to a row address applied to the row address circuit; a column address circuit adapted to select a column of memory cells in the array corresponding to a column address applied to the column address circuit; a data path circuit adapted to couple data between an external terminal and a memory cell in the row and column of the array corresponding to the row and column address applied to the row address circuit and the column address circuit, respectively; a command buffer adapted to receive a plurality of command packets each of which contain a plurality of command words, at least one of the command words containing at least one memory address; at least one command word register coupled to the command buffer, the command words being transferred from the command buffer to the command word register after the predetermined number of command words have been stored in the command buffer; an address pipeline having an input bus coupled to the command word register, the address pipeline having a plurality of address storage units each of which stores a respective memory address applied to the input bus responsive to a respective input enable signal, each of the address storage units applying its stored address to an output bus of the address pipeline responsive to a respective output enable signal; a control circuit selectively applying the respective input enable signals and output enable signals to each of the address storage units; and a memory address processing circuit coupled to the output bus of the address pipeline.

Claim 19

The memory device of claim 15, wherein the memory address processing unit comprises an address decoder.

Claim 20

The memory device of claim 15 further comprising a latch having an input bus coupled to the output bus of the address pipeline to receive each one of the memory addresses stored in the address storage units and an output bus coupled to the memory address processing circuit to process a memory address stored in the latch.

Claim 21

The memory device of claim 15 further comprising a plurality of address bus circuits each of which is coupled to a respective bit of the output bus, the bus circuits coupling the memory address from an enabled address storage unit to the memory address processing circuits.

Claim 22

The memory device of claim 18 wherein the address bus circuits each comprises a latch having an input coupled to a respective bit of the output bus and an output coupled to the memory address processing circuit.

Claim 23

The memory device of claim 15, further comprising an adder for allowing the storing and processing system to operate in a burst mode, the adder having an input bus coupled to the output bus of the address pipeline and an output bus coupled to the memory address processing circuit, the adder generating a series of addresses that increment from an initial address stored in the address pipeline.

Claim 24

The memory device of claim 15 wherein the memory addresses stored in each of the address storage units of the address pipeline comprise respective addresses of columns of memory cells in at least one memory array.

Claim 25

A computer system, comprising: processor having a processor bus; an input device coupled to the processor through the processor bus and adapted to allow data to be entered into the computer system; an output device coupled to the processor through the processor bus adapted to allow data to be output from the computer system; and a memory device coupled to the processor through the processor bus, comprising: at least one array of memory cells adapted to store data at a location determined by a row address and a column address; a row address circuit adapted to select a row of memory cells in the array corresponding to a row address applied to the row address circuit; a column address circuit adapted to select a column of memory cells in the array corresponding to a column address applied to the column address circuit, a data path circuit adapted to couple data between an external terminal and a memory cell in the row and column of the array corresponding to the row and column address applied to the row address circuit and the column address circuit, respectively; a command buffer adapted to receive a memory command to control the operation of the memory device; an address buffer adapted to receive row addresses and column addresses applied to the address buffer; an address pipeline having an input bus coupled to the address buffer, and a plurality of address storage units each of which stores a respective address applied to the input bus responsive to a respective input enable signal, each of the address pipelines applying its stored address to an output bus of the address pipeline responsive to a respective output enable signal; a memory address processing circuit coupled to the output bus of the address pipeline; and a control circuit selectively applying the respective input enable signals and output enable signals to each of the address storage units.

Claim 26

A computer system, comprising: processor having a processor bus; an input device coupled to the processor through the processor bus and adapted to allow data to be entered into the computer system; an output device coupled to the processor through the processor bus adapted to allow data to be output from the computer system; and a memory device coupled to the processor through the processor bus, comprising: at least one array of memory cells adapted to store data at a location determined by a row address and a column address; a row address circuit adapted to select a row of memory cells in the array corresponding to a row address applied to the row address circuit; a column address circuit adapted to select a column of memory cells in the array corresponding to a column address applied to the column address circuit, a data path circuit adapted to couple data between an external terminal and a memory cell in the row and column of the array corresponding to the row and column address applied to the row address circuit and the column address circuit, respectively; a command buffer adapted to receive a memory command to control the operation of the memory device; an address buffer adapted to receive row addresses and column addresses applied to the address buffer; an address pipeline having an input bus coupled to the address buffer, and a plurality of address storage units each of which stores a respective address applied to the input bus responsive to a respective input enable signal, each of the address pipelines applying its stored address to an output bus of the address pipeline responsive to a respective output enable signal; a memory address processing circuit coupled to the output bus of the address pipeline; and a control circuit selectively applying the respective input enable signals and output enable signals to each of the address storage units.

Claim 27

The computer system of claim 22, wherein the memory address processing unit comprises an address decoder.

Claim 28

The computer system of claim 22 further comprising a latch having an input bus coupled to the output bus of the address pipeline to receive each one of the memory addresses stored in the address storage units and an output bus coupled to the memory address processing circuit to process a memory address stored in the latch.

Claim 29

The computer system of claim 22 further comprising a plurality of address bus circuits each of which is coupled to a respective bit of the output bus, the bus circuits coupling the memory address from an enabled address storage unit to the memory address processing circuit.

Claim 30

The computer system of claim 25 wherein the address bus circuits each comprises a latch having an input coupled to a respective bit of the output bus and an output coupled to the memory address processing circuit.

Claim 31

The computer system of claim 22, further comprising an adder for allowing the memory device to operate in a burst mode, the adder having an input bus coupled to the output bus of the address pipeline and an output bus coupled to the memory address processing circuit, the adder generating a series of addresses that increment from an initial address stored in the address pipeline.

Claim 32

The computer system of claim 22 wherein the memory addresses stored in each of the address storage units of the address pipeline comprise respective addresses of columns of memory cells in the array of memory cells.

Claim 33

A computer system, comprising: a processor having a processor bus; an input device coupled to the processor through the processor bus and adapted to allow data to be entered into the computer system; an output device coupled to the processor through the processor bus adapted to allow data to be output from the computer system; and a memory device coupled to the processor through the processor bus, comprising: at least one array of memory cells adapted to store data at a location determined by a row address and a column address; a row address circuit adapted to select a row of memory cells in the array corresponding to a row address applied to the row address circuit; a column address circuit adapted to select a column of memory cells in the array corresponding to a column address applied to the column address circuit; a data path circuit adapted to couple data between an external terminal and a memory cell in the row and column of the array corresponding to the row and column address applied to the row address circuit and the column address circuit, respectively; a command buffer adapted to receive a plurality of command packets each of which contain a plurality of command words, at least one of the command words containing at least one memory address; at least one command word register coupled to the command buffer, the command words being transferred from the command buffer to the command word register after the predetermined number of command words have been stored in the command buffer; an address pipeline having an input bus coupled to the command word register, the address pipeline having a plurality of address storage units each of which stores a respective memory address applied to the input bus responsive to a respective input enable signal, cach of the address storage units applying its stored address to an output bus of the address pipeline responsive to a respective output enable signal; a control circuit selectively applying the respective input enable signals and output enable signals to each of the address storage units, and a memory address processing circuit coupled to the output bus of the address pipeline.

Claim 34

A computer system, comprising: a processor having a processor bus; an input device coupled to the processor through the processor bus and adapted to allow data to be entered into the computer system; an output device coupled to the processor through the processor bus adapted to allow data to be output from the computer system; and a memory device coupled to the processor through the processor bus, comprising: at least one array of memory cells adapted to store data at a location determined by a row address and a column address; a row address circuit adapted to select a row of memory cells in the array corresponding to a row address applied to the row address circuit; a column address circuit adapted to select a column of memory cells in the array corresponding to a column address applied to the column address circuit; a data path circuit adapted to couple data between an external terminal and a memory cell in the row and column of the array corresponding to the row and column address applied to the row address circuit and the column address circuit, respectively; a command buffer adapted to receive a plurality of command packets each of which contain a plurality of command words, at least one of the command words containing at least one memory address; at least one command word register coupled to the command buffer, the command words being transferred from the command buffer to the command word register after the predetermined number of command words have been stored in the command buffer; an address pipeline having an input bus coupled to the command word register, the address pipeline having a plurality of address storage units each of which stores a respective memory address applied to the input bus responsive to a respective input enable signal, cach of the address storage units applying its stored address to an output bus of the address pipeline responsive to a respective output enable signal; a control circuit selectively applying the respective input enable signals and output enable signals to each of the address storage units, and a memory address processing circuit coupled to the output bus of the address pipeline.

Claim 35

The computer system of claim 29, wherein the memory address processing unit comprises an address decoder.

Claim 36

The computer system of claim 29 further comprising a latch having an input bus coupled to the output bus of the address pipeline to receive each one of the memory addresses stored in the address storage units and an output bus coupled to the memory address processing circuit to process a memory address stored in the latch.

Claim 37

The computer system of claim 29 further comprising a plurality of address bus circuits each of which is coupled to a respective bit of the output bus, the bus circuits coupling the memory address from an enabled address storage unit to the memory address processing circuit.

Claim 38

The computer system of claim 32 wherein the address bus circuits each comprises a latch having all input coupled to a respective bit of the output bus and an output coupled to the memory address processing circuit.

Claim 39

The computer system of claim 29, further comprising an adder for allowing the storing and processing system to operate in a burst mode, the adder having an input bus coupled to the output bus of the address pipeline and an output bus coupled to the memory address processing circuit, the adder generating a series of addresses that increment from an initial address stored in the address pipeline.

Claim 40

The computer system of claim 29 wherein the memory addresses stored in each of the address storage units of the address pipeline comprise respective addresses of columns of memory cells in at least one memory array.

Claim 43

The method of claim 36 wherein the step of processing each of the stored memory addresses comprises selectively decoding each of the stored memory addresses.

Claim 44

The method of claim 36, further comprising the step of conveying the memory addresses over a common signal path from a location where the step of storing the memory address is performed to the location where the step of selectively processing each of the stored memory addresses is performed.

Claim 45

The method of claim 36 wherein the memory addresses comprise addresses designating a column of at least one array of memory cells.

Claim 46

The method of claim 36 further comprising latching each of the memory addresses one-at-a-time after the memory addresses have been stored in the memory device, and wherein the act of processing each of the stored memory addresses comprises processing each of the memory addresses after each of the memory addresses have been latched.

Claim 47

The method of claim 36 further comprising: latching one of the memory addresses after the memory address has been stored in the memory device; and sequentially incrementing the latched memory addresses to provide a plurality of memory addresses increasing in value from the latched memory address.

Claim 50

The method of claim 42 wherein the step of processing each of the packet word portions corresponding to respective memory addresses comprises selectively decoding each of the packet word portions.

Claim 51

The method of claim 42, further comprising the step of conveying the packet word portions over a common signal path from a location where the step of storing the packet word portions is performed to the location where the step of selectively processing each of the step of processing each of the packet word portions Is performed.

Claim 52

The method of claim 42 wherein the packet word portions comprises memory addresses designating a column of at least one array of memory cells.

Claim 53

The method of claim 42 further comprising latching each of the packet word portions one-at-a-time after the packet word portions have been stored, and wherein the act of processing each of the stored packet word portions comprises processing each of the packet word portions after each of the packet word portions have been latched.

Claim 54

The method of claim 42 further comprising: latching one of the packet word portions after the packet word portion has been stored; and sequentially incrementing the latched packet word portion to provide a plurality of memory addresses increasing in value from the memory address corresponding to the latched packet word portion.

Claim 57

The storing and processing system of claim 48, wherein the memory address processing unit comprises an address decoder.

Claim 58

The storing and processing system of claim 48 further comprising a latch having an input bus coupled to the output bus of the address pipeline to receive each one of the memory addresses stored in the address storage units and an output bus coupled to the memory address processing circuit to process a memory address stored in the latch.

Claim 59

The storing and processing system of claim 48 further comprising a plurality of address bus circuits each of which is coupled to a respective bit of the output bus, the bus circuits coupling the memory address from an enabled address storage unit to the memory address processing circuit.

Claim 60

The storing and processing system of claim 51 wherein the address bus circuits each comprises a latch having an input coupled to a respective bit of the output bus and an output coupled to the memory address processing circuit.

Claim 61

The storing and processing system of claim 48, further comprising an adder for allowing the storing and processing system to operate in a burst mode, the adder having an input bus coupled to the output bus of the address pipeline and an output bus coupled to the memory address processing circuit, the adder generating a series of addresses that increment from an initial address stored in the address pipeline.

Claim 62

The storing and processing system of claim 48 wherein the memory addresses stored in each of the address storage units of the address pipeline comprise respective addresses of columns of memory cells in at least one memory array.