Command encoded delayed clock generator

Claim 2

A clock feeding circuit to a semiconductor memory wherein said memory is comprised of separate independent control circuits each requiring a clock signal, comprising means for receiving a control signal applied to one of said control circuits, and means for applying a clock signal to said one of the independent control circuits, restricted to said one of the independent control circuits.

Claim 3

A clock feeding circuit as defined in claim 1 in which said control circuits are column and row predecoders.

Claim 4

A clock feeding circuit as defined in claim 2 further comprising means for applying a constant clock signal to circuits of said memory requiring said constant clock signals, but restricting application of the constant clock signals from application to other ones of said independent control circuits.

Claim 5

A clock feeding circuit as defined in claim 3 including means for providing each of the clock signals as delayed clock signals from an input clock signal.

Claim 6

A delayed clock generator comprising: (a) means for receiving memory command signals which are the same command signals for application to a semiconductor memory, (b) means for receiving an input clock signal, (c) means for generating a plurality of delayed clock signals from the input clock signal, (d) means for providing specific ones of said delayed clock signals to specific parts of said memory commanded by said command signals, upon reception of corresponding ones of said command signals commanding said specific parts of said memory.

Claim 7

A delayed clock generator comprising: (a) means for receiving memory command signals which are the same command signals for application to a semiconductor memory, (b) means for receiving an input clock signal, (c) means for generating a plurality of delayed clock signals from the input clock signal, (d) means for providing specific ones of said delayed clock signals to specific parts of said memory commanded by said command signals, upon reception of corresponding ones of said command signals commanding said specific parts of said memory.

Claim 8

A delayed clock generator as defined in claim 5 including further means for providing a delayed constant clock signal for application to a delayed clock input of said memory.

Claim 9

A delayed clock generator as defined in claim 6 in which said memory is a synchronous dynamic random access memory (SDRAM) in which the control signals are /CS, /RAS, /CAS, /WE and BA, and in which the providing means generate delayed clock signals in accordance with the following truth table: ______________________________________ /CS /RAS /CAS /WE BA Clocks f.sub.DCLK ______________________________________ H X X X X Disable 0 L X X X X DCLK.sub.-- CTRL fCLK L L H X X DCLK.sub.-- X One Pulse L H L X L DCL K.sub.-- Y0 f.sub.CLK /2 L H L X H DCLK.sub.-- Y1 f.sub.CLK /2 ______________________________________ where DCLK -- CTRL is the delayed constant clock signal, DCLK -- X is a delayed clock for application to x-predecoders of the SDRAM, DCLK -- Y0 is a delayed clock for application to one bank of y-predecoders of the SDRAM, DCLK -- Y1 is a delayed clock for application to another bank of y-predecoders of the SDRAM, fDCLK is the frequency of the delayed clock signal, and fCLK is the frequency of the input clock signal.