Patent US6144057A successfully refreshed from Google Patents.
US6144057A
Expired / Lapsed
US
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Semiconductor memory device including a field effect transistor
Assignee: Semiconductor Energy Laboratory Co Ltd
•
Filing: 1997-05-16
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Granted: 2000-11-07
•
Expires: 2017-05-16
Abstract
Abstract A semiconductor memory device including a field effect transistor associated with a semiconductor substrate and a capacitor. The capacitor is connected to a drain region of the transistor. Specifically, the capacitor includes a dielectric layer including a ferroelectric material. The capacitor is located above a gate electrode of the transistor and completely overlaps the gate electrode. The device may also include a pair of field effect transistors wherein each source of the transistors shares a common impurity doped region of the semiconductor substrate.
Inventors
- 👤 Shunpei Yamazaki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 01:55
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01332; H10D64/01336; H10D64/01342; C; C23; C23C; C23C14/00; C23C14/0021; C23C14/0036; C23C14/06; C23C14/0641; C23C14/0652; C23C14/08; C23C14/083; C23C14/088; H10D64/0134; H10D64/60; H10D64/66; H10D64/68; H10D64/691; H10D64/693; H10P; H10P14/00; H10P14/60; H10P14/63; H10P14/6326; H10P14/6328; H10P14/6329; H10P14/6334; H10P14/69; H10P14/692; H10P14/6938; H10P14/6939; H10P14/69393; H10P14/69394; H10P14/69398
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
135 words
A semiconductor memory device comprising: a semiconductor substrate; a pair of field effect transistors associated with said semiconductor substrate wherein each source of said transistors shares a common impurity doped region formed in a plateau elevated from said semiconductor substrate and each gate electrode of said transistors is formed over each channel region of said transistors; a first capacitor connected to a drain of one of said transistors; a second capacitor connected to a drain of another one of said transistors, wherein said each of said first and second capacitors comprises a pair of electrodes and a dielectric layer interposed therebetween, said dielectric layer comprising a ferroelectric material, and wherein each of said first and second capacitors is located over said gate electrode of the corresponding transistor so as to completely overlap said gate electrode.
Claim 2
Dependent Claim
135 words
A semiconductor memory device comprising: a semiconductor substrate; a pair of field effect transistors associated with said semiconductor substrate wherein each source of said transistors shares a common impurity doped region formed in a plateau elevated from said semiconductor substrate and each gate electrode of said transistors is formed over each channel region of said transistors; a first capacitor connected to a drain of one of said transistors; a second capacitor connected to a drain of another one of said transistors, wherein said each of said first and second capacitors comprises a pair of electrodes and a dielectric layer interposed therebetween, said dielectric layer comprising a ferroelectric material, and wherein each of said first and second capacitors is located over said gate electrode of the corresponding transistor so as to completely overlap said gate electrode.
Claim 3
Dependent Claim
24 words
A semiconductor memory device according to claim 1 wherein said ferroelectric material is selected from the group consisting of barium titanate and lead titanate.
Claim 4
Dependent Claim
108 words
A semiconductor memory device comprising: a semiconductor substrate; a pair of field effect transistors associated with said semiconductor substrate wherein each source of said transistors shares a common impurity doped region formed in a plateau elevated from said semiconductor substrate and each gate electrode of said transistors is formed over each channel region of said transistors; a first capacitor connected to a drain of one of said transistors; a second capacitor connected to a drain of another one of said transistors, and wherein each of said first and second capacitors is located over said gate electrode of the corresponding transistor so as to completely overlap said gate electrode.
Claim 5
Dependent Claim
108 words
A semiconductor memory device comprising: a semiconductor substrate; a pair of field effect transistors associated with said semiconductor substrate wherein each source of said transistors shares a common impurity doped region formed in a plateau elevated from said semiconductor substrate and each gate electrode of said transistors is formed over each channel region of said transistors; a first capacitor connected to a drain of one of said transistors; a second capacitor connected to a drain of another one of said transistors, and wherein each of said first and second capacitors is located over said gate electrode of the corresponding transistor so as to completely overlap said gate electrode.
Claim 6
Dependent Claim
32 words
A semiconductor memory device according to claim 3 wherein said each channel region of said transistors is formed in said semiconductor substrate and between said plateau and each of said drain regions.
Claim 7
Dependent Claim
175 words
A semiconductor memory device including at least first and second insulated gate field effect transistors, said device comprising: a semiconductor substrate having a first surface and a plateau elevated from said first surface; a first impurity region formed within said plateau as a source of both said first and second transistors; a pair of second impurity regions formed within said semiconductor substrate with said plateau disposed therebetween as drains of said first and second transistors, respectively; a pair of capacitors electrically connected to said pair of second impurity regions, respectively; a pair of channel regions formed within said substrate between said plateau and said pair of second impurity regions, respectively; and a pair of gate electrodes adjacent to said channel regions, respectively, wherein each of said first and second capacitors comprises a pair of electrodes and a dielectric layer interposed therebetween, said dielectric layer comprising a ferroelectric material, and wherein each of said first and second capacitors is located over said gate electrode of the corresponding transistor so as to completely overlap said gate electrode.
Claim 8
Dependent Claim
175 words
A semiconductor memory device including at least first and second insulated gate field effect transistors, said device comprising: a semiconductor substrate having a first surface and a plateau elevated from said first surface; a first impurity region formed within said plateau as a source of both said first and second transistors; a pair of second impurity regions formed within said semiconductor substrate with said plateau disposed therebetween as drains of said first and second transistors, respectively; a pair of capacitors electrically connected to said pair of second impurity regions, respectively; a pair of channel regions formed within said substrate between said plateau and said pair of second impurity regions, respectively; and a pair of gate electrodes adjacent to said channel regions, respectively, wherein each of said first and second capacitors comprises a pair of electrodes and a dielectric layer interposed therebetween, said dielectric layer comprising a ferroelectric material, and wherein each of said first and second capacitors is located over said gate electrode of the corresponding transistor so as to completely overlap said gate electrode.
Claim 9
Dependent Claim
23 words
A semiconductor device according to claim 5 wherein each of said capacitors extends beyond the associated channel region and the associated gate electrode.
Claim 10
Dependent Claim
138 words
A semiconductor memory device comprising: a semiconductor substrate; a pair of field effect transistors associated with said semiconductor substrate, each of which comprises source and drain regions, a channel region therebetween, and a gate electrode over the channel region wherein the source regions of the pair of field effect transistors are formed in a same impurity region in a plateau elevated from said semiconductor substrate; a first capacitor connected to a drain region of one of the drains of the pair of transistors; a second capacitor connected to the other one of the drains of the pair of transistors; wherein each of said first and second capacitor has a dielectric layer, and wherein each of said first and second capacitors is located over said gate electrode of the corresponding transistor so as to completely overlap said gate electrode.
Claim 11
Dependent Claim
138 words
A semiconductor memory device comprising: a semiconductor substrate; a pair of field effect transistors associated with said semiconductor substrate, each of which comprises source and drain regions, a channel region therebetween, and a gate electrode over the channel region wherein the source regions of the pair of field effect transistors are formed in a same impurity region in a plateau elevated from said semiconductor substrate; a first capacitor connected to a drain region of one of the drains of the pair of transistors; a second capacitor connected to the other one of the drains of the pair of transistors; wherein each of said first and second capacitor has a dielectric layer, and wherein each of said first and second capacitors is located over said gate electrode of the corresponding transistor so as to completely overlap said gate electrode.
Claim 12
Dependent Claim
15 words
The semiconductor memory device according to claim 7 wherein said dielectric layer comprises tantalum oxide.
Claim 13
Dependent Claim
15 words
The semiconductor memory device according to claim 7 wherein said dielectric layer comprises titanium oxide.
Claim 14
Dependent Claim
28 words
The semiconductor memory device according to claim 7 wherein said dielectric layer comprises a material selected from the group consisting of silicon nitride, tantalum nitride and titanium nitride.
Claim 15
Dependent Claim
30 words
The semiconductor memory device according to claim 7 wherein said dielectric layer comprises a material selected from the group consisting of tantalum oxide, titanium oxide, barium titanate and lead titanate.
Claim 16
Dependent Claim
168 words
A semiconductor memory device including at least first and second insulated gate field effect transistors, said device comprising: a semiconductor substrate having a first surface and a plateau elevated from said first surface; a first impurity region formed within said plateau as a source of both said first and second transistors; a pair of second impurity regions formed within said semiconductor substrate with said plateau disposed therebetween as drains of said first and second transistors, respectively; a pair of capacitors electrically connected to said pair of second impurity regions, respectively; a pair of channel regions formed within said substrate between said plateau and said pair of second impurity regions, respectively; and a pair of gate electrodes adjacent to said channel regions, respectively, wherein each of said first and second capacitors comprises a pair of electrodes and a dielectric layer interposed therebetween, and wherein each of said first and second capacitors is located over said gate electrode of the corresponding transistor so as to completely overlap said gate electrode.
Claim 17
Dependent Claim
168 words
A semiconductor memory device including at least first and second insulated gate field effect transistors, said device comprising: a semiconductor substrate having a first surface and a plateau elevated from said first surface; a first impurity region formed within said plateau as a source of both said first and second transistors; a pair of second impurity regions formed within said semiconductor substrate with said plateau disposed therebetween as drains of said first and second transistors, respectively; a pair of capacitors electrically connected to said pair of second impurity regions, respectively; a pair of channel regions formed within said substrate between said plateau and said pair of second impurity regions, respectively; and a pair of gate electrodes adjacent to said channel regions, respectively, wherein each of said first and second capacitors comprises a pair of electrodes and a dielectric layer interposed therebetween, and wherein each of said first and second capacitors is located over said gate electrode of the corresponding transistor so as to completely overlap said gate electrode.
Claim 18
Dependent Claim
15 words
The semiconductor memory device according to claim 12 wherein said dielectric layer comprises tantalum oxide.
Claim 19
Dependent Claim
15 words
The semiconductor memory device according to claim 12 wherein said dielectric layer comprises titanium oxide.
Claim 20
Dependent Claim
28 words
The semiconductor memory device according to claim 12 wherein said dielectric layer comprises a material selected from the group consisting of silicon nitride, tantalum nitride and titanium nitride.
Claim 21
Dependent Claim
126 words
A semiconductor memory device comprising: a semiconductor substrate; a pair of field effect transistors associated with said semiconductor substrate wherein each source of said transistors shares a common impurity region formed in plateau elevated from said semiconductor substrate and each gate electrode of said transistors is formed over each channel region of said transistors; a first capacitor connected to a drain of one of said transistors; a second capacitor connected to a drain of another one of said transistors, wherein each of said first and second capacitors comprises a pair of electrodes and a tantalum oxide layer interposed therebetween, and wherein each of said first and second capacitors is located over said gate electrode of the corresponding transistor so as to completely overlap said gate electrode.
Claim 22
Dependent Claim
126 words
A semiconductor memory device comprising: a semiconductor substrate; a pair of field effect transistors associated with said semiconductor substrate wherein each source of said transistors shares a common impurity region formed in plateau elevated from said semiconductor substrate and each gate electrode of said transistors is formed over each channel region of said transistors; a first capacitor connected to a drain of one of said transistors; a second capacitor connected to a drain of another one of said transistors, wherein each of said first and second capacitors comprises a pair of electrodes and a tantalum oxide layer interposed therebetween, and wherein each of said first and second capacitors is located over said gate electrode of the corresponding transistor so as to completely overlap said gate electrode.
Claim 23
Dependent Claim
31 words
A semiconductor memory device according to claim 16 wherein each channel region of said transistors is formed in said semiconductor substrate and between said plateau and each of said drain regions.
Claim 24
Dependent Claim
129 words
A semiconductor memory device comprising: a semiconductor substrate; a pair of field effect transistors associated with said semiconductor substrate wherein each source of said transistors shares a common impurity region formed in plateau elevated from said semiconductor substrate and each gate electrode of said transistors is formed over each channel region of said transistors; a first capacitor connected to a drain region of said drain regions of said pair of transistors; a second capacitor connected to the other one of said drains of said pair of transistors; wherein each of said first and second capacitors has a dielectric layer comprising tantalum oxide, and wherein each of said first and second capacitors is located over said gate electrode of the corresponding transistor so as to completely overlap said gate electrode.
Claim 25
Dependent Claim
129 words
A semiconductor memory device comprising: a semiconductor substrate; a pair of field effect transistors associated with said semiconductor substrate wherein each source of said transistors shares a common impurity region formed in plateau elevated from said semiconductor substrate and each gate electrode of said transistors is formed over each channel region of said transistors; a first capacitor connected to a drain region of said drain regions of said pair of transistors; a second capacitor connected to the other one of said drains of said pair of transistors; wherein each of said first and second capacitors has a dielectric layer comprising tantalum oxide, and wherein each of said first and second capacitors is located over said gate electrode of the corresponding transistor so as to completely overlap said gate electrode.
Claim 26
Dependent Claim
31 words
A semiconductor memory device according to claim 18 wherein each channel region of said transistors is formed in said semiconductor substrate and between said plateau and each of said drain regions.
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2003-11-07 | 2004-05-08 | 2004-11-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-11-07 | 2008-05-08 | 2008-11-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-11-07 | 2012-05-08 | 2012-11-07 | $7700.00 | Window Closed / Lapsed |