Pointer based DMA controller

Claim 1

A direct memory access controller for controlling access of a host and a disk device to a buffer memory, wherein data transfer through said buffer memory between said host and disk device is controlled by first and second signals, respectively, during separate disk read and write cycles, whenever data are transferred between the host and the disk device and processed by an error correction device, said first and second signals each being in a respective one of at least two states, said direct memory access controller comprising: (A) pointer means for providing: (1) an access address HP of the host to the buffer memory, said access address HP defining an address in said buffer memory at which a data transfer with said host is made, (2) an access address DP of the disk device to the buffer memory, said access address DP defining an address in said buffer memory at which a data transfer with said disk device is made, (3) an address CP offset by a predetermined amount from said address HP, said address CP being an address in said buffer memory which differs from said access address HP by said predetermined amount, (4) an address GP in said buffer memory of a data block of a predetermined size processed by said error correction device, said address GP defining an address in said buffer memory at which said data block processed by said error correction device is stored; (B) comparing means coupled to said pointer means for comparing HP with GP and for comparing DP with CP; (C) port state solver means responsive to said comparing means for changing the states of said first and second signals whenever HP and GP are equal and whenever DP and CP are equal, respectively; and (D) cycle and direction control means for: (1) incrementing by said predetermined amount said address GP in said pointer means whenever said error correction device processes one data block of said predetermined size, (2) incrementing said addresses HP and DP in said pointer means by a size corresponding to one data unit whenever a data unit is transferred between said buffer memory and one of said host and disk device, respectively, and (3) starting data transfer if currently stopped or stopping data transfer if currently on-going between said buffer memory and one of said host and disk device in response to a change in the state of a respective one of said first and second signals.

Claim 9

A method of controlling the access of a host and disk device to a buffer memory, wherein data transfer through said buffer memory between said host and disk device is controlled by first and second signals, respectively, during separate disk read and write cycles, whenever data are transferred between the host and the disk device and processed by an error correction device, said first and second signals each being in a respective one of at least two states, said method comprising: (A) providing in individual pointer registers: (1) an access address HP of the host to the buffer memory, said access address HP defining an address in said buffer memory at which a data transfer with said host is made, (2) an access address DP of the disk device to the buffer memory, said access address DP defining an address in said buffer memory at which a data transfer with said disk device is made, (3) an address CP offset by a predetermined amount from said address HP, said address CP being an address in said buffer memory which differs from said access address HP by said predetermined amount, (4) an address GP in said buffer memory of a data block of a predetermined size processed by said error correction device, said address GP defining an address in said buffer memory at which said data block processed by said error correction device is stored; (B) comparing HP with GP and comparing DP with CP; (C) changing the states of said first and second signals whenever HP and GP are equal and whenever DP and CP are equal, respectively, as determined in said comparing step; (D) incrementing by said predetermined amount said address GP whenever said error correction device processes one data block of said predetermined size; (E) incrementing said addresses HP and DP by a size corresponding to one data unit whenever a data unit is transferred between said buffer memory and one of said host and disk device, respectively; and (F) starting data transfer if currently stopped or stopping data transfer if currently on-going between said buffer memory and one of said host and disk device whenever a respective one of said first and second signals changes state.

Claim 10

A method of controlling the access of a host and disk device to a buffer memory, wherein data transfer through said buffer memory between said host and disk device is controlled by first and second signals, respectively, during separate disk read and write cycles, whenever data are transferred between the host and the disk device and processed by an error correction device, said first and second signals each being in a respective one of at least two states, said method comprising: (A) providing in individual pointer registers: (1) an access address HP of the host to the buffer memory, said access address HP defining an address in said buffer memory at which a data transfer with said host is made, (2) an access address DP of the disk device to the buffer memory, said access address DP defining an address in said buffer memory at which a data transfer with said disk device is made, (3) an address CP offset by a predetermined amount from said address HP, said address CP being an address in said buffer memory which differs from said access address HP by said predetermined amount, (4) an address GP in said buffer memory of a data block of a predetermined size processed by said error correction device, said address GP defining an address in said buffer memory at which said data block processed by said error correction device is stored; (B) comparing HP with GP and comparing DP with CP; (C) changing the states of said first and second signals whenever HP and GP are equal and whenever DP and CP are equal, respectively, as determined in said comparing step; (D) incrementing by said predetermined amount said address GP whenever said error correction device processes one data block of said predetermined size; (E) incrementing said addresses HP and DP by a size corresponding to one data unit whenever a data unit is transferred between said buffer memory and one of said host and disk device, respectively; and (F) starting data transfer if currently stopped or stopping data transfer if currently on-going between said buffer memory and one of said host and disk device whenever a respective one of said first and second signals changes state.