US4963504A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for fabricating double implanted LDD transistor self-aligned with gate
Assignee: Xerox Corp
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Filing: 1989-11-24
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Granted: 1990-10-16
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Expires: 2009-11-24
Abstract
Abstract An improved double implanted and aligned LDD transistor comprising a gate having a central alignment member and a pair of outboard alignment members having portions contiguous with the gate oxide layer. A lightly doped junction is aligned with the central alignment member and a heavily doped junction is aligned with the outboard alignment members.
Inventors
- 👤 Tiao-Yuan Huang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 06:55
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D30/60; H10D30/601; H10D30/605; H10D30/0212
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
171 words
A method for fabricating LDD transistor devices comprising the steps of: providing a semiconductor substrate of a first conductivity type, forming a gate insulating film on said semiconductor substrate, forming a thin conductive layer upon said gate insulating film, forming a thick alignment member upon said thin conductive layer, doping said substrate to a first impurity concentration through said thin conductive layer, in alignment with said thick alignment member, with an impurity having a conductivity type opposite to that of said semiconductor substrate, so as to form a first doped region, depositing sidewall spacers upon said thin conductive layer on either side of said thick alignment member, doping said substrate to a second impurity concentration, higher than said first impurity concentration, in alignment with said sidewall spacers, with an impurity having a conductivity type opposite to that of said semiconductor substrate, so as to form a second doped region removing portions of said thin conductive layer outboard of said sidewall spacers, and thermally treating the substrate for electrically activating said impurities.
Claim 2
Independent Claim
171 words
A method for fabricating LDD transistor devices comprising the steps of: providing a semiconductor substrate of a first conductivity type, forming a gate insulating film on said semiconductor substrate, forming a thin conductive layer upon said gate insulating film, forming a thick alignment member upon said thin conductive layer, doping said substrate to a first impurity concentration through said thin conductive layer, in alignment with said thick alignment member, with an impurity having a conductivity type opposite to that of said semiconductor substrate, so as to form a first doped region, depositing sidewall spacers upon said thin conductive layer on either side of said thick alignment member, doping said substrate to a second impurity concentration, higher than said first impurity concentration, in alignment with said sidewall spacers, with an impurity having a conductivity type opposite to that of said semiconductor substrate, so as to form a second doped region removing portions of said thin conductive layer outboard of said sidewall spacers, and thermally treating the substrate for electrically activating said impurities.
Claim 3
Dependent Claim
27 words
The method as defined in claim 1 characterized in that said step of removing is performed before said step of doping said substrate to a second conductivity.
Claim 4
Dependent Claim
27 words
The method as defined in claim 1 characterized in that said step of removing is performed after said step of doping said substrate to a second conductivity.
Claim 5
Dependent Claim
19 words
The method as defined in claim 2 characterized in that said dopants are electrically activated by rapid thermal annealing.
Claim 6
Dependent Claim
19 words
The method as defined in claim 3 characterized in that said dopants are electrically activated by rapid thermal annealing.
Claim 7
Dependent Claim
135 words
The method as defined in claim 1 characterized in that said steps of forming a thin conductive layer and forming a thick alignment member comprise: depositing a first conductive layer whose thickness is the same as said thin conductive layer, upon said gate insulating film; depositing plural layers having differential etch characteristics to an aggregate thickness which is the same as said thick alignment member, the layer adjacent to said first conductive layer having an etch characteristic different from said first conductive layer; masking the surface of said plural layers in the area to be formed into said thick alignment member; and sequentially totally removing the unmasked portions of said surface layer and the layers thereunder, by means of different etchants, in areas outboard of said thick alignment member, stopping at said thin conductive layer.
Claim 8
Dependent Claim
75 words
The method as defined in claim 1 characterized in that said steps of forming a thin conductive layer and forming a thick alignment member comprise: depositing a conductive layer whose thickness is the same as said thick alignment member, upon said gate insulating film; masking said conductive layer in the area to be formed into said thick alignment member; and removing portions of said unmasked conductive layer on either side of said thick alignment member.
Claim 9
Dependent Claim
92 words
The method as defined in claim 1 characterized in that said steps of forming a thin conductive layer and forming a thick alignment member comprise: depositing a first conductive layer whose thickness is the same as said thin conductive layer, upon said gate insulating film; depositing a second conductive layer whose thickness is the same as said thick alignment member; masking said second conductive layer in the area to be formed into said thick alignment member; and totally removing portions of said unmasked second conductive layer outboard of said thick alignment member.
Claim 10
Dependent Claim
88 words
The method as defined in claim 1 characterized in that said steps of forming a thin conductive layer and forming a thick alignment member comprise: depositing a conductive layer whose thickness is the same as said thin conductive layer, upon said gate insulating film; depositing an insulating layer whose thickness is the same as said thick alignment member; masking said insulating layer in the area to be formed into said thick alignment member; and totally removing portions of said unmasked insulating layer outboard of said thick alignment member.
Claim 11
Dependent Claim
114 words
The method as defined in claim 1 characterized in that said steps of forming a thin conductive layer and forming a thick alignment member comprise: depositing a first conductive layer whose thickness is the same as said thin conductive layer, upon said gate insulating film; masking said first conductive layer with a negatively patterned photoresist layer having a notch whose dimensions are equal to the dimensions of said thick alignment member; depositing a second conductive layer whose thickness is the same as said thick alignment member over said photoresist layer; and lifting off said photoresist layer bearing said second conductive layer, so as to leave said thick alignment member upon said first conductive layer.
Claim 12
Dependent Claim
32 words
The method as defined in claim 6 characterized in that a silicide layer is formed on the surface of said thick alignment member and the substrate surface of said second doped region.
Claim 13
Dependent Claim
32 words
The method as defined in claim 7 characterized in that a silicide layer is formed on the surface of said thick alignment member and the substrate surface of said second doped region.
Claim 14
Dependent Claim
32 words
The method as defined in claim 8 characterized in that a silicide layer is formed on the surface of said thick alignment member and the substrate surface of said second doped region.
Claim 15
Dependent Claim
32 words
The method as defined in claim 9 characterized in that a silicide layer is formed on the surface of said thick alignment member and the substrate surface of said second doped region.
Claim 16
Dependent Claim
32 words
The method as defined in claim 10 characterized in that a silicide layer is formed on the surface of said thick alignment member and the substrate surface of said second doped region.
References Cited (Backward Citations)
US4818715A
Cited
US4837180A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1993-10-15 | 1994-04-16 | 1994-10-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-10-15 | 1998-04-16 | 1998-10-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-10-15 | 2002-04-16 | 2002-10-16 | $7700.00 | Window Closed / Lapsed |