US4883543A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Shielding for implant in manufacture of dynamic memory
Assignee: Texas Instruments Inc
•
Filing: 1980-06-05
•
Granted: 1989-11-28
•
Expires: 2000-06-05
Abstract
Abstract A method for making semiconductor devices such as dynamic read/write memory cell arrays of the one-transistor N- channel silicon gate type employs an ion implant of high dosage to produce N+ source/drain regions. The transistor and capacitor gates are in place when this implant is performed, and the chain oxide beneath the gates can break down due to static charge produced on the slice surface as a result of the ion implant. To prevent build-up of static charge on the surface, a thin coating of polysilicon is applied before the implant and grounded. This coating is subsequently removed by thermal oxidation or etching. Alternatively, a thermal oxide coating may be used as it will prevent the implanted arsenic from reaching the polysilicon gates, although it will penetrate a thinner thermal oxide coating over the source/drain area. Other dielectric films such as silicon nitride may also be used.
Inventors
- 👤 Richard N. Gossen, Jr.
- 👤 William C. Bruncke
- 👤 Gordon D. Baker
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 18:56
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/05; H10P; H10P30/00; H10P30/20; H10P30/22
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
135 words
A method of making a semiconductor device such as an array of memory cells of the one-transistor type, comprising the step of: applying conductive areas such as transistor gates and capacitor gates to a face of a semiconductor body separated from the face by a thin dielectric, wherein the body is P-type silicon, and the conductive areas include conductive material which is polycrystalline silicon, coating said entire face with a thin layer of insulating material which acts as a shield against electrostatic build-up on said conductive areas, subjecting said face to an ion implant to create heavily doped N+ semiconductor regions in said face, wherein said implant is arsenic, wherein said step of coating includes thermal oxidation, the thickness of the coating being much greater over said polycrystalline silicon than over exposed single crystal silicon.
Claim 2
Independent Claim
135 words
A method of making a semiconductor device such as an array of memory cells of the one-transistor type, comprising the step of: applying conductive areas such as transistor gates and capacitor gates to a face of a semiconductor body separated from the face by a thin dielectric, wherein the body is P-type silicon, and the conductive areas include conductive material which is polycrystalline silicon, coating said entire face with a thin layer of insulating material which acts as a shield against electrostatic build-up on said conductive areas, subjecting said face to an ion implant to create heavily doped N+ semiconductor regions in said face, wherein said implant is arsenic, wherein said step of coating includes thermal oxidation, the thickness of the coating being much greater over said polycrystalline silicon than over exposed single crystal silicon.
Claim 3
Dependent Claim
20 words
A method according to claim 1 wherein said ion implant does not penetrate the insulating coating over said polycrystalline silicon.
Claim 4
Dependent Claim
38 words
A method according to claim 1 wherein the step of applying conductive areas include: applying a second layer of conductive material on said face partially overlying the first layer and insulated therefrom, and overlying a second semiconductor region.
Claim 5
Dependent Claim
21 words
A method according to claim 3 wherein the second layer is patterned to define isolated conductor segments which are electrically floating.
Claim 6
Dependent Claim
22 words
A method according to claim 4 wherein the first layer is patterned to define an elongated gate for a plurality of capacitors.
Claim 7
Independent Claim
132 words
A method of making a semiconductor device comprising the steps of: coating an entire face of a semiconductor body with a thin layer of shield material, subjecting said face to a high dosage ion implant which penetrates said layer in some selected areas to form regions in said face and which does not penetrate said layer in other selected areas, wherein a conductive layer of polycrystalline silicon has been previously applied to said other selected areas, wherein the step of coating with shield material creates a barrier to build-up electrostatic charge on said conductive layer during said ion implant and includes subsequently thermally oxidizing the layer and the surface above said regions, and wherein the step of coating includes forming thicker oxide on the polycrystalline silicon than on exposed single crystal silicon.
Claim 8
Independent Claim
132 words
A method of making a semiconductor device comprising the steps of: coating an entire face of a semiconductor body with a thin layer of shield material, subjecting said face to a high dosage ion implant which penetrates said layer in some selected areas to form regions in said face and which does not penetrate said layer in other selected areas, wherein a conductive layer of polycrystalline silicon has been previously applied to said other selected areas, wherein the step of coating with shield material creates a barrier to build-up electrostatic charge on said conductive layer during said ion implant and includes subsequently thermally oxidizing the layer and the surface above said regions, and wherein the step of coating includes forming thicker oxide on the polycrystalline silicon than on exposed single crystal silicon.
References Cited (Backward Citations)
US4240092A
Cited
US4208781A
Cited
US4270262A
Cited
US4224733A
Cited
US4290184A
Cited
US4230504A
Cited
US4230504B1
Cited
US4326329A
Cited
US4334236A
Cited
US4240195A
Cited
US4317274A
Cited
US4282646A
Cited
US4350536A
Cited
US4326331A
Cited
US4350992A
Cited
US4325169A
Cited
US4305200A
Cited
US4364167A
Cited
US4388121A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-11-27 | 1993-05-29 | 1993-11-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-11-27 | 1997-05-29 | 1997-11-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-11-27 | 2001-05-29 | 2001-11-28 | $7700.00 | Window Closed / Lapsed |