N-Channel silicon gate virtual ground ROM

Claim 1

A read only memory array comprising: a plurality of memory cells formed at a face of a silicon body in an array of rows and columns; each memory cell including an insulated gate field effect transistor having a source, a drain and a polysilicon gate, the gate being insulated from the silicon by a thin gate insulator for selected ones of the memory cells; and interconnections to the sources and drains formed by column lines partially underlying row lines on the face, the row lines being polysilicon strips generally perpendicular to the column lines and forming said gates, thick field oxide underlying the gate for remaining memory cells other than said selected ones of the memory cells to alter substantially the threshold of the transistors of such remaining cells compared to the transistors of said selected ones of the memory cells, the thick field oxide extending into said face to a depth greater than that of said thin gate insulator, said column lines including diffused regions self-alligned with the row lines and heavily doped implanted regions underlying the row lines and extending out from beneath the row lines to spaces between the rows lines, the diffused regions and the implanted regions together creating continuous conductive paths to form the column lines, the thick field oxide being formed in said face between the column lines but not overlying the column lines.