Reduced field implant for dynamic memory cell array

Claim 1

A method of making a dynamic semiconductor memory cell of the one-transistor type comprising the steps of: masking a face of a silicon body to expose field areas and cover transistor and capacitor areas, subjecting said face to an impurity ion implant at a dosage of not more than about 3×10 12 atoms per sq. cm. to produce implanted regions in said field areas but not in said transistor and capacitor areas, annealing said body in an inert atmosphere after said implant, thereafter growing field oxide in said field areas by exposing said face to an oxidizing atmosphere at high temperature thereby creating lightly doped channel stop regions from said implanted regions, forming electrodes at said transistor and capacitor areas to provide a memory cell, wherein the step of forming electrodes includes: applying a first layer of conductive material over said face of the semiconductor body to form a capacitor electrode overlying a first semiconductor region, applying a second layer of conductive material on said face partially overlying the first layer and overlying a second semiconductor region, the first and second semiconductor regions including said capacitor and transistor areas, respectively, applying a metal layer to said face to define at least one elongated strip overlying the first and second layers and making contact to at least one of said electrodes.

Claim 2

A method of making a dynamic semiconductor memory cell of the one-transistor type comprising the steps of: masking a face of a silicon body to expose field areas and cover transistor and capacitor areas, subjecting said face to an impurity ion implant at a dosage of not more than about 3×10 12 atoms per sq. cm. to produce implanted regions in said field areas but not in said transistor and capacitor areas, annealing said body in an inert atmosphere after said implant, thereafter growing field oxide in said field areas by exposing said face to an oxidizing atmosphere at high temperature thereby creating lightly doped channel stop regions from said implanted regions, forming electrodes at said transistor and capacitor areas to provide a memory cell, wherein the step of forming electrodes includes: applying a first layer of conductive material over said face of the semiconductor body to form a capacitor electrode overlying a first semiconductor region, applying a second layer of conductive material on said face partially overlying the first layer and overlying a second semiconductor region, the first and second semiconductor regions including said capacitor and transistor areas, respectively, applying a metal layer to said face to define at least one elongated strip overlying the first and second layers and making contact to at least one of said electrodes.